MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 137

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
16.1.6 Interrupt Mask Registers (Y40 - Y4F) Bit Functions
Tables 109 to 115 describe the bit functions of each of the Interrupt Mask Registers in the MT9072. Each
register is repeated for each of the 4 framers (not the Interrupt Vector Mask). Framer 0 is addressed with Y=0,
Framer 1 with Y=1, Framer 2 with Y=2. and Framer 7 with Y=7 (where Y represents the 4 most significant
address bits (MSB) A11 A10 A9 A8). In addition, a simultaneous write to all 8 Framers is possible by setting the
A11 address to Y=8 (1000). A (0) or (1) in the “Name” column of these tables indicates the state of the data bits
after a hard reset (the RESET pin is toggled from zero to one), or a software reset (the RST bit in control
register address YF1 is toggled from one to zero) or a T1E0 write to the Global Control Register bit 15.
15-9
Bit
Bit
15
14
13
8
7
6
5
4
3
2
1
0
TXUNDERIM
RXOVFLIM
EOPDIM
EOPRIM
TEOPIM
RXFFIM
CRCOIM
OOFOIM
TXFLIM
FEOIM
Name
GAIM
Name
FAIM
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
Table 110 - Receive and Sync Interrupt Mask Register(Y44) (T1)
not used.
Go Ahead Interrupt Mask. When unmasked an interrupt is generated when go-ahead
pattern (01111111) was detected by the HDLC receiver.
End of Packet Data Interrupt Mask. When unmasked an interrupt is initiated when an end
of packet (EOP) byte was written into the RX FIFO by the HDLC receiver.
Transmit End of Packet Interrupt Mask. When unmasked an interrupt is initiated when
the transmitter has finished sending the closing flag of a packet or after a packet has been
aborted.
End of Packet Received Interrupt Mask. When unmasked an interrupt is initiated when
the byte about to be read from the RX FIFO is the last byte of the packet. An interrupt is
also initiated if the Rx FIFO is read and there is no data in it.
Transmit Fifo Low Interrupt Mask. When unmasked an interrupt is initiated when the Tx
FIFO is emptied below the selected low threshold level.
Frame Abort: Transmit Interrupt Mask. When unmasked an interrupt is initiated this bit
(FA) is set when a frame abort is received during packet reception. It must be received after
a minimum number of bits have been received (26) otherwise it is ignored.
Transmit Fifo Underrun Interrupt Mask. When unmasked an interrupt is initiated for TX
FIFO underrun indication.
Receive Fifo full Threshold interrupt Mask. When unmasked an interrupt is initiated
whenever the Rx FIFO is filled above the 16 byte threshold level.
Receive Fifo Overflow Interrupt Mask. When unmasked an interrupt is initiated
whenever the 32 byte RX FIFO overflowed (i.e. an attempt to write to a 32 byte full RX
FIFO).
Framing Bit Error Counter Overflow Interrupt Mask. When unmasked an interrupt is
initiated whenever the framing bit error counter changes from FFH to 00H. 1 -masked, 0 -
unmasked.
CRC-6 Error Counter Overflow Interrupt Mask. When unmasked an interrupt is initiated
whenever the CRC-6 error counter changes from FFH to 00H. 1 - masked, 0 - unmasked.
Out Of Frame Counter Overflow Interrupt Mask. When unmasked an interrupt is
initiated whenever the out of frame counter changes state from changes from FFH to 00H.
1 - masked, 0 - unmasked.
Table 109 - HDLC Interrupt Mask Register(Y43) (T1)
Functional Description
Functional Description
MT9072
137