MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 28

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Table 20 -Receive PCM30 National Bits to ST-BUS 2.048Mbit/s or 8.192Mbit/s DSTo (E1)................................ 60
Table 21 -T1.403 and T1.408 Message Oriented Performance Report Structure (T1) ......................................... 61
7.0
Table 22 - Registers Related to Signaling (T1) ..................................................................................................... 63
Table 23 -Registers Related to CAS Signaling (E1).............................................................................................. 64
Table 24 -Channel Associated Signaling (CAS) Multiframe Structure (E1)........................................................... 65
Table 25 -Transmit PCM30 CAS Channels 1 to 30 from ST-BUS 2.048Mbit/s or 8.192Mbit/s CSTi (E1) ............ 66
Table 26 -Receive PCM30 CAS Channels 1 to 30 to ST-BUS 2.048Mbits or 8.192Mbits CSTo (E1) .................. 66
Table 27 -Transmit PCM30 CCS from ST-BUS 2.048Mbit/s or 8.192Mbit/s CSTi (E1) ........................................ 67
Table 28 -Transmit PCM30 CCS from ST-BUS 2.048Mbit/s or 8.192Mbit/s DSTi (E1) ........................................ 67
Table 29 -Receive PCM30 CCS to ST-BUS 2.048Mbit/s or 8.192Mbit/s CSTo (E1) ............................................ 68
Table 30 -Receive PCM30 CCS to ST-BUS 2.048Mbit/s or 8.192Mbit/s DSTo (E1) ............................................ 68
Table 31 -CCS (Timeslot 15, 16 & 31) Source and Destination Summary Table (E1).......................................... 69
8.0
Table 32 - HDLC Related Registers ...................................................................................................................... 70
Table 33 - HDLC Frame Format............................................................................................................................ 71
xxviii
6.3
7.1
7.2
8.1
7.1.1
7.1.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.1.7
8.1.8
8.1.9
Signaling ........................................................................................................................ 62
7.2.2.1..................... E1 Channel Associated Signaling (CAS) Transmit from ST-BUS CSTi to PCM30 66
7.2.2.2..................... E1 Channel Associated Signaling (CAS) Receive from PCM30 to ST-BUS CSTo 66
T1 Signaling ........................................................................................................................................... 62
HDLC Description................................................................................................................................... 70
........................................................................................................................T1 Bit Oriented Message60
E1 Signaling .......................................................................................................................................... 63
T1 Robbed Bit Signaling.................................................................................................................. 62
T1 Common Channel Signaling....................................................................................................... 63
E1 Channel Associated Signaling (CAS) Register and ST-BUS Access ........................................ 65
E1 Common Channel Signaling (CCS) Transmit from ST-BUS CSTi and DSTi to PCM30 ............ 66
E1 Common Channel Signaling (CCS) Receive from PCM30 to CSTo and DSTo......................... 67
CCS (Timeslot 16) Programming Options Summary Table............................................................. 69
HDLC Frame Structure.................................................................................................................... 71
Data Transparency (Zero Insertion/Deletion) .................................................................................. 71
Invalid Frames ................................................................................................................................. 71
Frame Abort..................................................................................................................................... 71
Interframe Time Fill and Link Channel States ................................................................................. 72
Go-Ahead ........................................................................................................................................ 72
Functional Description ..................................................................................................................... 72
HDLC Transmitter............................................................................................................................ 72
HDLC Receiver................................................................................................................................ 73
Channel Associated Signaling (CAS) Operation ............................................................................ 63
Table of Contents (continued)
Advance Information
HDLC70