MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 94

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
cleared. After all interrupt status registers are cleared, the interrupt vector is cleared causing the IRQ pin to return
to a high impedance state.
If a new unmasked interrupt occurs while the interrupt status registers from a previous interrupt are being read,
the affected interrupt status registers will be updated, the interrupt vector will be updated, and the IRQ pin will
remain low until all interrupt status registers are cleared.
If the interrupt status registers are unmasked, and the interrupt vector is masked, the interrupt status registers
will function normally, but they will not cause the IRQ pin to toggle low. Only set bits in the Interrupt Vector will
cause the IRQ pin to toggle low. This is similar to the SPND control bit function, but instead of masking all
selected framer interrupts, the interrupt vector mask can mask individual registers within the selected framers.
14.1.1
SPND - All interrupts for a particular framer may be suspended without changing the interrupt mask words, by
setting the
to be updated (and will be cleared when read), but the selected framers interrupt vector bits will remain at zero.
Therefore that framer cannot toggle the IRQ pin. If all eight framer’s SPND bit are zero, then all interrupt vector bits
will remain low, therefore none of the framers can toggle the IRQ pin.
In some applications, a logic low at the IRQ pin lasting the full duration of the interrupt service routine may be
undesirable. In these cases, immediately following the interrupt, set the control bit SPND (register address
YF1) low until the interrupt service routine is finished
INTA - All interrupt and latched status registers for a particular framer may be cleared (without reading the
interrupt status registers) by setting the INTA control bit (register address YF1) to zero. Interrupt status and
latched registers for a particular framer will be cleared (and not updated) as long as INTA is low. Consequently,
the selected framer’s interrupt vector bits will remain at zero, therefore that framer cannot toggle the IRQ pin.
TAIS - During initial power up, all (8 framers) interrupt status registers are cleared without changing the
interrupt mask words, when the TAIS control pin is held low. Consequently, the interrupt vector will remain clear
and the IRQ pin will remain in a high impedance state. This allows for system initialization without spurious
interrupts. Interrupt status registers will not be updated, and the IRQ pin will be forced to a high impedance state
as long as TAIS is low.
RESET or RST - After a MT9072 reset (RESET pin for all eight framers or RST control bit (register address
YF1) for a selected framer), all interrupt status register bits are unmasked, but the SPND and INTA control bits
are set to zero.
14.2 Interrupt Servicing Methods
There are two common methods for identifying the source of an interrupt. The Polling Method is the simplest
but uses the most processor time. The Vector Method requires a two step process, but uses the least amount
of processor time.
14.2.1
1. The IRQ pin goes low.
2. Read all 33 interrupt vector status registers. The bits which are set in these registers identify the source of
the interrupt. As each register is read, it is cleared (all bits set to 0). When all registers are clear, the interrupt is
cleared (the IRQ pin returns to logic high) and all sources of the interrupt are identified.
14.2.2
1. The IRQ pin goes low.
2. Read the interrupt vectors. These vectors identify which of the 33 (or which combination of 33) interrupt
status registers has bits which are set. Note that if multiple framers (i.e. Framer 1 and 7), or multiple conditions
(i.e. Sync and Counter Overflow) caused the interrupt, more than one register may need to be read.
94
Interrupt Related Control Bits and Pins
Polling Method
Vector Method
SPND
control bit (register address YF1) to zero. All unmasked interrupt status registers will continue
Advance Information