MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 38

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
1.0
The MT9072 is an eight port (octal) framing device that can be software configured for T1, E1 or J1 operation.
Each of the eight framers can be independently timed and controlled. Each framer features one embedded
HDLC (High-level Data Link Controller) that can be assigned to the maintenance channel or to any other
channel.
1.1
In T1 mode, the MT9072 meets or supports the latest recommendations including AT&T PUB43801, TR-62411,
ANSI T1.102, T1.403 and T1.408. It also supports Telcordia GR-303-CORE. In T1 ESF mode the CRC-6
calculation and yellow alarm can be configured to meet the requirements of a J1 interface.
In E1 mode, the MT9072 meets or supports the latest ITU-T Recommendations for PCM30 and ISDN primary
rate including G.703, G.704, G.706, G.732, G.775, G.796, G.823, G.965 (V5.2) and I.431. It also meets or
supports ETSI TBR4, TBR13, ETS 300 233, and ETS 300 347 (V5.2).
1.2
A 16-bit parallel Motorola or Intel non-multiplexed microprocessor interface is used to access the control and
status registers.
1.3
On the line side the MT9072 framers interface to physical layer devices (typically LIUs) using a Return to Zero
(RZ) or Non Return to Zero (NRZ) protocol. The data can be single rail or dual rail with several T1 and E1 line
coding options available.
In T1 mode, the receive and transmit paths each include a two-frame slip buffer. The transmit slip buffer
features programmable delay and it serves as a rate converter between the ST-BUS and the 1.544Mbit/s T1
line rate.
In E1 mode, the receive path includes a two-frame slip buffer.
1.4
On the system side the MT9072 framers can interface to a 2.048Mbit/s or 8.192Mbit/s ST-BUS backplane, or a
2.048 Mbit/s GCI backplane.
There is an IMA (Inverse MUX for ATM) mode for IMA applications, this enables the framer to interface to a
1.544Mbit/s (T1) or 2.048Mbit/s (E1) serial bus with asynchronous transmit and receive timing.
1.5
The MT9072 framers operate in termination mode or transparent mode. In the receive transparent mode, the
received line data is channelled to the DSTo pin with arbitrary frame alignment. In the transmit transparent
mode, no framing or signaling is imposed on the data transmitted from the DSTi pin onto the line.
In T1 mode the framers operate in any of the following framing modes: D4, Extended Superframe (ESF) or
T1DM.
In E1 mode the framers run three framing algorithms: basic frame alignment, signalling multiframe alignment
and CRC-4 multiframe alignment. The Remote Alarm Indication (RAI) bit is automatically controlled by an
internal state machine.
38
Standards Compliance
Microprocessor Port
Interface to the Physical Layer Device
Interface to the System Backplane
Framing Modes
Overview
Advance Information