MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 52

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
(NFAS) is checked. If bit 2 of the NFAS is zero a new search for basic frame alignment is initiated. If bit 2 of the
NFAS is one and the next FAS is correct, the algorithm declares that basic frame synchronization has been
found (status register address Y10 bit BSYNC is reset to zero).
Once basic frame alignment is acquired the signaling and CRC-4 multiframe searches will be initiated. The
signaling multiframe algorithm will align to the first multiframe alignment signal pattern (MFAS = 0000) it
receives in the most significant nibble of channel 16 (status register address Y10 bit MSYNC is zero). Signaling
multiframe alignment will be lost when two consecutive multiframes are received in error.
The CRC-4 multiframe alignment signal is a 001011 bit sequence that appears in PCM30 bit position one of the
NFAS in frames 1, 3, 5, 7, 9 and 11 (see Table 12). In order to achieved CRC-4 synchronization two
consecutive CRC-4 multiframe alignment signals must be received without error (status register address Y10
bit CSYNC is zero).
The MT9072 framing algorithm supports automatic interworking of interfaces with and without CRC-4
processing capabilities. That is, if an interface with CRC-4 capability, achieves valid basic frame alignment, but
does not achieve CRC-4 multiframe alignment by the end of a predefined period, the distant end is considered
to be a non-CRC-4 interface. When the distant end is a non-CRC-4 interface, the near end automatically
suspends receive CRC-4 functions, continues to transmit CRC-4 data to the distant end with its E-bits set to
zero, and provides a status indication. Naturally, if the distant end initially achieves CRC-4 synchronization,
CRC-4 processing will be carried out by both ends. This feature is selected when control bit AUTC (control
register address Y00) is set to zero.
4.2.4.1 Notes for Synchronization State Diagram (Figure 7)
1) The basic frame alignment, signaling multiframe alignment, and CRC-4 multiframe alignment functions
2) The receive channel associated signaling bits and signaling multiframe alignment bit will be frozen when
3) Manual re-framing of the receive basic frame alignment and signaling multiframe alignment functions can be
4) The transmit RAI bit will be one until basic frame alignment is established, then it will be zero.
5) E-bits can be optionally set to zero until the equipment interworking relationship is established. When this
6) All manual re-frames and new basic frame alignment searches start after the current frame alignment signal
7) After basic frame alignment has been achieved, loss of frame alignment will occur any time three
8) When CRC-4 multiframe alignment has been achieved, the primary basic frame alignment and resulting
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operate in parallel and are independent.
multiframe alignment is lost.
performed at any time.
has been determined one of the following will take place:
position.
consecutive incorrect basic frame alignment signals are received. Loss of basic frame alignment will reset
the complete framing algorithm.
multiframe alignment will be adjusted to the basic frame alignment determined during CRC-4
synchronization. Therefore, the primary basic frame alignment will not be updated during the CRC-4
multiframe alignment search, but will be updated when the CRC-4 multiframe alignment search is complete.
a) CRC-to-non-CRC operation - E-bits = 0,
b) CRC-to-CRC operation - E-bits as per G.704 and I.431.
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