MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 45

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
4.1.1
For D4 links the S-bit position contains an alternating 101010... pattern inserted into every second S-bit. These
bits are intended for determination of frame boundaries, and they are referred to as Ft bits. A separate fixed
pattern, repeating every superframe, is interleaved with the Ft bits. This fixed pattern (001110) is used to
delineate the 12 frame superframe. These bits are referred to as the Fs bits. In D4 frames # 6 and #12, the LSB
of each channel byte may be replaced with A bit (frame #6) and B bit (frame #12) signaling information. See
Table 8.
Register
Address
Y1A
Y2A
Y2B
Y2C
Y00
Y10
Y16
Y17
Y19
Y24
Y28
Y34
Y44
T1 D4 Framing
Framing Mode Select
Synchronization and Alarm
Status Word.
MFOOF Counter
Framing Bit Error Counter
CRC-6 Error Counter
Out of Frame Counter and
Change of Frame Counter
Receive Sync and Alarm Latch
Framing Bit Error Count Latch
CRC-6 Error Counter Latch
Out of Frame Counter Latch and
Change of Frame Counter Latch
MFOOF Counter Latch
Receive Sync Interrupt Status
Register
Receive Sync Interrupt Status
Register Mask
Table 7 - Registers Related to Framing Mode for the MT9072 (T1)
Register
This register is used for selecting the different framing modes
from ESF to D4 or T1DM. The register is also used for selecting
reframe criteria.
This register provides the real time status of the receive framing
algorithm as to basic frame synchronization and multiframe
synchronization.
This status register increments every 1.5 msec for D4 mode or
every 3 msec for ESF mode when the basic frame
synchronization is lost.
This counter counts the Ft errors in ESF mode and Ft+Fs error in
D4 and T1DM.
This counter counts the CRC-6 errors by comparing the
calculated CRC-6 with the CRC-6 bits in the ESF frame.
The out of frame counter is incremeted with every loss of receive
frame synchronization. The change of frame counter is
incremented with every shift in the frame alignment position.
This register contains latched bits for events related to framing
such as framing bit errors.
This counter is a latched version of Y17, the value of this counter
is updated every 1 sec.
This counter is a latched version of Y19, the value of this counter
is updated ever 1 sec.
This counter is a latched version of Y19, the value of this counter
is updated ever 1 sec.
This counter is a latched version of Y16, the value of this counter
is updated ever 1 sec.
This register captures interrupt events related to the receiver
framer such as Framing Bit error. Interrupts can be generated by
setting appropriate masks.
This mask corresponds to the Y34 status register. Writing a “0”
unmasks an interrupt.
Description
MT9072
45