MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 53

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
5.0
The MT9072 has a two frame receive elastic (or slip) buffer, which absorbs wander and low frequency jitter in
multi-trunk applications. If desired, the elastic buffer can be bypassed by using the Data Link RxDL pin output
(see the following section). The received data (RPOS and RNEG) is clocked into the elastic buffer with the
extracted (EXCLi pin) clock and is clocked out of the elastic buffer with the system (CKi pin) clock. The EXCLi
clock is generated from the receive data, and is therefore phase-locked with that data. In normal operation, the
EXCLi clock will be phase-locked to the CKi clock by an external phase locked loop (PLL). Therefore, in a
single trunk system, the receive data is in phase with the EXCLi clock, the CKi clock is phase-locked to the
EXCLi clock, and the read and write positions of the elastic buffer will remain fixed with respect to each other.
* only if CRC-4 synchronization is selected and
** only if automatic CRC-4 interworking is selected.
automatic CRC-4 interworking is de-selected.
Elastic Buffer
CRC-to-CRC interworking. Re-align to new
>914 CRC errors
processing. E-bits set as per G.704 and
in one second
CRC multiframe
I.431. Indicate CRC synchronization
basic frame alignment. Start CRC-4
CRC-4 multi-frame
alignment
alignment
No CRC multiframe
Start 400 msec timer.
Find two CRC frame
Start 8 msec timer.
alignment signals.
8 msec. timer
alignment.
expired*
Notes 7 & 8.
achieved.
Note 7.
Note 7.
Note 7.
Figure 7 - Synchronization State Diagram (E1)
NO
alignment acquired
synchronization acquired. Enable
Basic frame
traffic RAI=0, E’s=0. Start loss of
primary basic frame alignment
8 msec. timer
Verify Bit 2 of non-frame
Search for primary basic
checking. Notes 7 & 8.
frame alignment signal
expired**
Out of synchronization
Primary basic frame
occurrence of frame
alignment signal.
alignment signal.
multiframe
alignment.
RAI=1, Es=0.
No CRC
Verify second
RAI = 0
primary basic frame alignment. Continue
CRC-to-non-CRC interworking. Maintain
processing. E-bits set to ‘0’. Indicate
CRC-to-non-CRC operation. Note 7.
to send CRC-4 data, but stop CRC
Parallel search for new basic
YES
YES
YES
YES
frame alignment signal.
NO
NO
Notes 6 & 7.
Check for two consecutive errored
400 msec timer expired
multiframe alignment signals.
Multiframe synchronization
acquired as per G.732.
Search for multiframe
NO
NO
alignment signal.
Notes 7 & 8.
signaling multi-frame
Note 7.
Note 7.
alignment
YES
3 consecutive incorrect
frame alignment
YES
signals
MT9072
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