MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 196

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
16.2.6
Tables 129 and 130 describes the bit functions of the Interrupt Vectors, while Tables 182 to 185 describe the bit
functions of each of the Interrupt Status Registers in the MT9072. Each interrupt status register is repeated for
each of the 8 framers (not the Interrupt Vectors). Framer 0 is addressed with Y=0, Framer 1 with Y=1, Framer
2 with Y=2 and so on up to Framer 7 with Y=7 (where Y represents the 4 most significant address bits (MSB)
A11-A8). However, since the Interrupt Vectors are common for all eight framers, only addresses 910 and 911
may be used to read from these registers. The (#) indicates that the unused bit position may be read as either
a (0) or (1).
196
15-9
Bit
8
7
6
5
4
3
2
1
0
Interrupt Vector and Interrupt Status Registers (Y3X) Bit Functions
TXUNDERI
RXOVFLI
EOPDI
EOPRI
TEOPI
RXFFI
Name
TXFLI
GAI
FAI
#
not used.
Go Ahead Interrupt. Indicates a go-ahead pattern (01111111) was detected by the
HDLC receiver. This bit is reset after a read.
End of Packet Data Interrupt.This bit is set when an end of packet (EOP) byte was
written into the RX FIFO by the HDLC receiver. This can be in the form of a flag, an
abort sequence or as an invalid packet. This bit is reset after a read.
Transmit End of Packet Interrupt.This bit is set when the transmitter has finished
sending the closing flag of a packet or after a packet has been aborted. This bit is reset
after read.
End of Packet Receive Fifo Interrupt.This bit is set when the byte about to be read
from the RX FIFO is the last byte of the packet. It is also set if the Rx FIFO is read and
there is no data in it. This bit is reset after a read.
Transmit FIFO Low Interrupt.This bit is set when the Tx FIFO is emptied below the
selected low threshold level. This bit is reset after a read.
Frame Abort: Transmit Interrupt. this bit (FA) is set when a frame abort is received
during packet reception. It must be received after a minimum number of bits have been
received (26) otherwise it is ignored.
Transmit Elastic Buffer Empty Interrupt. If high it Indicates that a read by the
transmitter was attempted on an empty Tx FIFO. This bit is reset after a read.
Receive FIFO is filled above Threshold Interrupt.This bit is set when the Rx FIFO is
filled above the selected full threshold level. This bit is reset after a read.
Receive FiFO Overflow Interrupt. This bit Indicates that the 32 byte RX FIFO
overflowed (i.e. an attempt to write to a 32 byte full RX FIFO). The HDLC will always
disable the receiver once the receive overflow has been detected. The receiver will be
re-enabled upon detection of the next flag, but will overflow again unless the RX FIFO
is read. This bit is reset after a read.
Table 182 - HDLC Interrupt Status Register(Y33) (E1)
Functional Description
Advance Information