MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 59

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
6.2.1.3 E1 Data Link (DL) Pin Data Received on PCM30 - With Elastic Buffer
In this case, the TxDLC pin is used for both DL data transmitted on the PCM30 link and DL data received on
the PCM30 link. However, instead of using the non-buffered data output at the RxDL pin, the buffered DSTo
output data is used. The clock at the TxDLC pin clocks data from the DSTo ST-BUS stream into an external
controller, or the enable signal at the TxDLC pin enables a 2.048Mbit/s clock which clocks data from the DSTo
ST-BUS stream into an external controller. Since a common clock is used for both transmit and receive, a
simpler data controller may be used such as the MT8952B. However, DL data will be lost or repeated when a
receive frame slip occurs, as the DL data does pass through the elastic buffer. See Figures 59 - 60 for timing
requirements.
6.2.2
When the National Bit Buffer transmit data registers access is enabled, the settings of 40 data bits in 5
registers (address YB0-YB4) determine the Data Link (DL) output on the PCM30 link corresponding to bit
positions Sa4-8 over one complete CRC-4 Multiframe. The CRC-4 alignment status bit CALN (register address
Y11) and corresponding maskable interrupt status bit CALNI (register address Y36) indicate the beginning of
every received CRC-4 multiframe. Data for DL transmission should be written to the National Bit Buffer transmit
data registers immediately following the CALN status indication (during basic frame 0) and before the start of
basic frame 1.
Table 18 illustrates the organization of the MT9072 transmit and receive national bit buffers. Each row is an
addressable byte of the MT9072 national bit buffer, and each column contains the national bits of an odd
numbered frame of each CRC-4 Multiframe. The transmit and receive national bit buffers are located at
addresses YB0 to YB4 and YC0 to YC4 respectively.
For the National Bit Buffer transmit registers DL access to be enabled the SA4SS to SA8SS(register Y08) are
set to 00.
Similarly, the DL data received on the PCM30 link is output to the National Bit Buffer receive data registers
(register address YC0-YC4), corresponding to bit positions as shown in Table 18. However, the National Bit
Buffer receive data registers are always enabled, regardless of the above control bit settings(SA4SS to
SA8SS). Received DL Data should be read from the National Bit Buffer receive data registers immediately
following the CALN status indication (during basic frame 0) and before the start of basic frame 1.
In order to facilitate conformance to ETS 300 233, three maskable interrupts are available for change of state
of Sa bits in the receive National Bit Buffer. These include Eight Consecutive Sa6 Nibbles (Sa6N8), Sa6 Nibble
Change (Sa6N) and Sa Nibble Change (SaN). See the detailed descriptions for these status bits provided in
the CAS, National, CRC-4 Local and Timer Interrupt Status Register (address Y36).
6.2.3
When the ST-BUS Data Link (DL) access is enabled, the setting of the 8 ST-BUS DSTi data bits determine the
Data Link (DL) output on the PCM30 link corresponding to bit positions one to three and Sa4-8 over each Non-
Transmit
TN0
TN1
TN2
TN3
TN4
E1 Data Link (DL) National Bit Buffer Access
E1 Data Link (DL) ST-BUS Access
Address
Addressable Bytes
YB0
YB1
YB2
YB3
YB4
Table 18 - MT9072 National Bit Buffers (E1)
Receive
RN0
RN1
RN2
RN3
RN4
Address
YC0
YC1
YC2
YC3
YC4
B7
F1
S
S
S
S
S
a4
a5
a6
a7
a8
NFAS Frames of a CRC-4 Multiframe
B6
S
S
S
S
S
F3
a4
a5
a6
a7
a8
B5
S
S
S
S
S
F5
a4
a5
a6
a7
a8
B4
S
S
S
S
S
F7
a4
a5
a6
a7
a8
B3
S
S
S
S
S
F9
a4
a5
a6
a7
a8
F11
B2
S
S
S
S
S
a4
a5
a6
a7
a8
MT9072
F13
B1
S
S
S
S
S
a4
a5
a6
a7
a8
F15
B0
S
S
S
S
S
a4
a5
a6
a7
a8
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