MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 102

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
15.4.2
The Bypass Register is a single stage shift register that provides a one-bit path from TDI to TDO.
The Boundary-Scan Register (BSR) provides an interface between the MT9072 core logic and the MT9072
input and output pins. This interface is controlled by the TAP Controller and Instruction Register. The BSR
provides status of all input, output and bi-directional pins and control over all output and bi-directional pins. The
BSR maps to 192 pins. Each input pin maps to one BSR bit (input cell), each output pin maps to one or two
BSR bits (output and enable cells), and each bi-directional pin maps to three BSR bits (input, output and
enable cells). Bit 0 of the BSR is the last bit in the JTAG chain and the first bit clocked out. The JTAG chain
starts at RPOS[0] and moves counterclockwise around the chip finishing at the T1 pin. See Table 55 for
additional details.
15.5 Boundary Scan Description Language (BSDL) File
A Boundary Scan Description Language (BSDL) file is available for the MT9072 JTAG implementation. This
ASCII (text) file provides all the information required for a JTAG test system to access the MT9072’s boundary
scan circuitry.
102
RNEG[0]
EXCLi[0]
RPOS[0]
TPOS[0]
CSTo[0]
Name
R/W
IRQ
D15
D14
T1
T3
The Bypass Register
Device Pin
bi-directional 22-24
bi-directional 25-27
This sequence continues around the chip. Refer to the BSDL file for BSR bit mapping.
This sequence continues around the chip. Refer to the BSDL file for BSR bit mapping.
This sequence continues around the chip. Refer to the BSDL file for BSR bit mapping.
This sequence continues around the chip. Refer to the BSDL file for BSR bit mapping.
output
output
output
output
Type
input
input
input
input
input
Cell #
227-
228
242
243
244
245
0
1
6
7
When this control/status bit is
one, the corresponding pin is
in a high impedance state.
When zero, the corresponding
pin operates normally.
Table 55 - JTAG Boundary-Scan Register
Enable Cell
227
NA
NA
NA
NA
NA
NA
NA
NA
22
25
Boundary-Scan Register Bits (0 to 245)
When this control/status
bit is one, the
corresponding pin is high.
When zero, the
corresponding pin is low.
Output Cell
228
242
NA
NA
NA
NA
NA
NA
23
26
6
Advance Information
When this status bit
is one, the
corresponding pin is
high. When zero,
the corresponding
pin is low.
Input Cell
243
244
245
NA
NA
NA
24
27
0
1
7