MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 267
![no-image](/images/no-image-200.jpg)
MT9072
Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9072.pdf
(278 pages)
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Preliminary Information
AC Electrical Characteristics - Receive Basic Frame and E4o Timing
ST-BUS
Bit Cells
2Mb/s
ST-BUS
Bit Cells
8Mb/s
FPi
(ST-BUS F0i)
Internal
(ST-BUS C2)
CKi
(ST-BUS C4i)
FPi
(ST-BUS F16i)
CKi
(ST-BUS C16i)
TxDLC - Note 2
(Output)
TxDLC - Note 3
(Output)
TxDL
(Input)
(2Mb/s)
TxDLC - Note 2
(Output)
TxDLC - Note 3
(Output)
Note 1 - TxDLC output applies for every second frame (FPi) pulse (250us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
1
2
3
3
Basic Frame Output Delay
Clock Delay
E4o Clock High Width
E4o Clock Low Width
76543210
Characteristics
Bit
Bit
TS124
7
7
Bit
Sa4 to Sa8 clocked in by MT9072
Sa4 to Sa8 clocked in by MT9072
Example A - 20 kbit/s clock output
Example A - enable output
Example B - 12 kbit/s clock output
Sa4, Sa7 and Sa8 clocked in by MT9072
Example B - enable output
Sa4, Sa7 and Sa8 clocked in by MT9072
Bit
6
Bit
6
76543210
Bit
5
Bit
5
TS125
Bit
Timeslot 31
Figure 71 - Transmit Data Link Pin Functional Timing
Bit
4
Bit
4
76543210
Bit
3
Bit
3
TS126
Bit
Bit
2
Bit
2
76543210
Bit
Bit
1
TS127
1
Bit
t
Sym
t
Bit
Bit
E4HW
0
E4LW
0
t
t
BD
CD
76543210
Bit
Bit
7
7
TS0
Bit
Bit
6
Bit
6
Min
30
50
25
76543210
Bit
5
Bit
5
Timeslot 0
TS1
Bit
Bit
Sa4
Bit
4
Typ
76543210
Bit
Sa5
Bit
3
Bit
TS2
Bit
Sa6
Bit
2
Max
115
200
55
75
76543210
Bit
Bit
Sa7
1
Bit
TS3
Units
Bit
Bit
Sa8
0
ns
ns
ns
ns
76543210
Bit
Bit
7
7
Bit
TS4
Timeslot 1
150pF load on RxBF
150pF load on RxDLC
150pF load on RxDLC
150pF load on RxDLC
Bit
6
Bit
6
76543210
Bit
5
Test Conditions
Bit
5
Bit
TS5
Bit
4
Bit
4
MT9072
267
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