MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 32

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Table 80 -Synchronization and Alarm Status Word(Y10) (T1) ............................................................................ 122
Table 81 -Timer Status Word(Y11) (T1) .............................................................................................................. 123
Table 82 -Receive Bit Oriented Message(Y12) (T1) ........................................................................................... 123
Table 84 -Transmit Slip Buffer Status Word(Y14) (T1)........................................................................................ 124
Table 83 -Receive Slip Buffer Status Word(Y13) (T1)......................................................................................... 124
Table 85 -PRBS Error Counter and CRC Multiframe Counter for PRBS(Y15) (T1) ............................................ 125
Table 86 -Multiframe Out of Frame Counter(Y16) (T1) ....................................................................................... 125
Table 87 -Framing Bit Error Counter(Y17) (T1)................................................................................................... 125
Table 88 -Bipolar Violation Counter(Y18) (T1) .................................................................................................... 125
Table 89 -CRC-6 Error Counter(Y19) (T1) .......................................................................................................... 125
Table 90 -Out of Frame and Change of Frame Counters(Y1A) (T1)................................................................... 125
Table 91 -Excessive Zero Counters(Y1B) (T1) ................................................................................................... 126
Table 92 - Transmit Byte Counter Position and HDLC Test Status(Y1C) (T1).................................................... 126
Table 93 -HDLC Status Word(Y1D) (T1)............................................................................................................. 127
Table 94 -HDLC Receive CRC(Y1E) (T1) ........................................................................................................... 127
Table 95 - Receive FIFO(Y1F) (T1)..................................................................................................................... 127
Table 96 -HDLC Status Latch(Y23) (T1) ............................................................................................................. 128
Table 97 -Receive Sync and Alarm Latch(Y24) (T1)........................................................................................... 129
Table 98 -Receive Line Status and Timer Latch(Y25) (T1) ................................................................................. 130
Table 100 -Framing Bit Error Count Latch(Y28) (T1) .......................................................................................... 131
Table 101 - Bipolar Violation Count Latch(Y29) (T1)........................................................................................... 131
Table 102 -CRC-6 Error Count Latch(Y2A) (T1) ................................................................................................. 131
Table 99 -Elastic Store and Excessive Zero Status Latch(Y26) (T1) .................................................................. 131
Table 103 -Out of Frame Count and Change of Frame Count Latch(Y2B) (T1) ................................................. 132
Table 104 - Multiframe Out of Frame Count Latch(Y2C) (T1) ............................................................................. 132
Table 105 -HDLC Interrupt Status Register(Y33) (T1) ........................................................................................ 133
Table 106 -Receive Synchronization and Alarm Interrupt Status Register(Y34) (T1) ......................................... 134
Table 107 -Receive Line and Timer Interrupt Status (Y35) (T1) ......................................................................... 135
Table 108 -Elastic Store and Excessive zero Interrupt Status Register(Y36) (T1).............................................. 136
Table 109 -HDLC Interrupt Mask Register(Y43) (T1).......................................................................................... 137
Table 110 -Receive and Sync Interrupt Mask Register(Y44) (T1)....................................................................... 137
Table 111 -Receive Line and Timer Interrupt Mask Register(Y45) (T1).............................................................. 139
Table 112 -Elastic Store and Excessive zero Interrupt Mask Register(Y46) (T1) ............................................... 139
Table 113 -Per Channel Transmit Signaling Y50-Y67 (T1) ................................................................................. 140
Table 114 -Per Channel Receive Signaling Y70-Y87 (T1) .................................................................................. 141
Table 115 -Per Channel Control Word(Y90-YA7) (T1)........................................................................................ 142
Table 116 -Interrupt and I/O Control(YF1) (T1) ................................................................................................... 143
Table 117 -HDLC Control 1(YF2) (T1) ................................................................................................................ 144
Table 118 -HDLC Test Control(YF3) (T1) ........................................................................................................... 145
Table 119 -Address Recognition Register(YF4) (T1) .......................................................................................... 146
Table 120 -TX Fifo Write Register(YF5) (T1) ...................................................................................................... 146
xxxii
16.1.4 Latched Status Registers (Y20 - Y2F) Bit Functions ..................................................................... 128
16.1.5
16.1.6
16.1.7 Per Channel Control and Data (Y50 - YAF) Bit Functions............................................................. 140
16.1.8 Master Control Registers (YF1 to YF7) Bit Functions ................................................................... 143
Interrupt Status Registers (Y30 - Y3F) Bit Functions.................................................................... 133
Interrupt Mask Registers (Y40 - Y4F) Bit Functions ..................................................................... 137
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