MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 55

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
5.1
In T1 mode, the MT9072 contains a transmit elastic buffer in addition to the receive elastic buffer. Data is
clocked into the transmit elastic buffer by the 2.048 Mbit/s or 8.192 Mbit/s ST-BUS clock (which is subsequently
divided to a 2.048MHz clock). The data is clocked out of the transmit elastic buffer by the 1.544MHz clock input
to the TXCL pin.
The delay through the transmit elastic buffer will vary in accordance with the position of the channel in the
frame. For example, PCM24 channel 1 sits in the elastic buffer for approximately 1 usec, and PCM24 channel
24 sits in the elastic buffer for approximately 32 usec. The relative phase delay between the system ST-BUS
frame boundary and the transmit elastic frame read boundary is measured every frame and reported in the
Transmit Slip Buffer Status Word (Y14). In addition, the relative delay between these frame boundaries may be
Register
Address
Register
Address
YF7
Y00
Y13
Y14
Y26
Y36
Y46
Y00
Y03
Y10
Y14
Y34
Y44
Transmit Elastic Buffer
Framing Mode Select
Receive Slip Buffer Status Word
Transmit Slip Buffer Status Word This register provides status bit for transmit slip and its direction
Elastic Store and Excessive Zero
Status Latch
Elastic Store and Excessive Zero
Interrupt Status
Elastic Store and Excessive Zero
Interrupt Mask
Transmit Set Delay Bits
Framing Mode Select
DL,CCS,CAS and Other
Control Register
Sync and CRC-4 Remote
status
Phase Status Indicator
Sync,CRC-4 Remote, Alarm,
MAS and Phase Status Word
Sync,CRC-4 Remote, Alarm,
MAS and Phase Status Word
Interrupt Mask
Register
Table 14 - Registers Related to the Elastic Buffer (T1)
Register
Table 15 - Registers Related to Elastic Store (E1)
If IMA mode is selected the transmit and receive elastic buffers
are bypassed.
This register provides status bits for receive slip and its direction
word that indicates the phase difference between the ST-BUS
and the PCM24
word that indicates the phase difference between the ST-BUS
and the PCM24.
This register indicates the latched version of the slip indicator
bits from registers Y13 and Y14.
Interrupt status word for the slip indicators.
Interrupt mask bits for the slip indicators.
This register sets a one time delay through the transmit slip
buffer.
If IMA mode is selected the receive elastic buffers are bypassed.
ELAS bit is used to bypass the elastic store, that data at DSTo is
the received. PCM30 data after the HDB3 coding.
RSLP and RSLPD show the slip and the direction of the slip.
This word reflects the delay through the receive elastic store
from the line to the ST-BUS side.
RSLIPI in this register reflects the interrupt due to a slip.
Interrupt mask bits for the slip indicator.
Description
Description
MT9072
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