MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 202
MT9072
Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9072.pdf
(278 pages)
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Table 187 - Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Mask Register (Address
Bit
15
14
13
12
10
11
9
8
7
6
5
4
RCRCRM
RCRC0M
RCRC1M
AUXPM
AIS16M
RSLPM
LOSSM
CEFSM
Name
RAIM
AISM
YM
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
#
not used.
Remote CRC-4 and RAI Mask. This is the mask bit for the RCRCRI interrupt status bit in the
Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address
Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Receive Slip Mask. This is the mask bit for the RSLPI interrupt status bit in the Sync (Sync,
CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address Y34). If this
mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit is zero, the
corresponding interrupt bit will function normally.
Receive Y-bit Mask. This is the mask bit for the YI interrupt status bit in the Sync (Sync,
CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address Y34). If this
mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit is zero, the
corresponding interrupt bit will function normally.
Auxiliary Pattern Mask. This is the mask bit for the AUXPI interrupt status bit in the Sync
(Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address Y34). If
this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit is zero,
the corresponding interrupt bit will function normally.
Remote Alarm Indication Status Mask. This is the mask bit for the RAII interrupt status bit in
the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address
Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Alarm Indication Status Signal Mask. This is the mask bit for the AISI interrupt status bit in
the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address
Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Alarm Indication Signal 16 Status Mask. This is the mask bit for the AIS16I interrupt status
bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register
(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this
mask bit is zero, the corresponding interrupt bit will function normally.
Loss of Signal Status Indication Mask. This is the mask bit for the LOSSI interrupt status bit
in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register
(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this
mask bit is zero, the corresponding interrupt bit will function normally.
Remote CRC-4 and RAI T10 Mask. This is the mask bit for the RCRC0I interrupt status bit in
the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register (address
Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this mask bit
is zero, the corresponding interrupt bit will function normally.
Remote CRC-4 and RAI T450 Mask. This is the mask bit for the RCRC1I interrupt status bit
in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Status Register
(address Y34). If this mask bit is one, the corresponding interrupt bit will remain inactive. If this
mask bit is zero, the corresponding interrupt bit will function normally.
Consecutively Errored Frame Alignment Signal Mask. This is the mask bit for the CEFSI
interrupt status bit in the Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt
Status Register (address Y34). If this mask bit is one, the corresponding interrupt bit will
remain inactive. If this mask bit is zero, the corresponding interrupt bit will function normally.
Y44) (E1)
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