MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 199

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Table 184 - Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1)
Bit
8
7
6
5
4
3
2
1
0
Name
PCOI
VEOI
EEOI
PEOI
CEII
VEII
EEII
PEII
#
CRC-4 Error Counter Indication Interrupt. This bit is one when the corresponding latched
status bit (CEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(CEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Bipolar Violation (BPV) Error Counter Overflow Interrupt. This bit is one when the
corresponding latched status bit (VEOL, register address Y25) is set, and the corresponding
mask bit is unmasked (VEOM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
Bipolar Violation (BPV) Error Counter Indication Interrupt. This bit is one when the
corresponding latched status bit (VEIL, register address Y25) is set, and the corresponding
mask bit is unmasked (VEIM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
E-Bit Error Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (EEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(EEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
E-Bit Error Counter Indication Interrupt. This bit is one when the corresponding latched
status bit (EEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(EEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
PRBS CRC-4 Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (PCOL, register address Y25) is set, and the corresponding mask bit is unmasked
(PCOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
not used.
PRBS Error Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (PEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(PEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
PRBS Error Counter Indication Interrupt. This bit is one when the corresponding latched
status bit (PEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(PEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Functional Description
MT9072
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