MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 188

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
188
15-0
7 - 0
Bit
5-4
3-2
1-0
Bit
Bit
6
RCRC15-0
RXFIFO7-0
RXSTAT1-0 Receive FIFO Status:
TXSTAT1-0 Transmit FIFO Status:
Name
RQ9-8
Name
Name
IDC
Received CRC. The CRC received from the transmitter. The LSB of the FCS sequence is
MSB in this register. This register is updated at the end of each received packet and
therefore should be read when end of packet is detected.
Idle Channel State. Is set to a 1 when an idle Channel state (15 or more ones) has been
detected at the receiver. This is an asynchronous event. On power reset, this may be 1 if
the clock (RXC) was not operating. Status becomes valid after the first 15 bits or the first
zero is received.
RQ9-8 Byte Status bits from RX FIFO. These bits determine the status of the byte to be
read from RX FIFO as follows:
00 Packet Byte
01 First Byte
10 Last byte of good packet
11 Last byte of bad packet
00 Transmit FIFO is full.
01 The number of bytes in the transmit FIFO has reached or exceeded 16 bytes
10 Transmit FIFO is empty
11 The number of bytes in the TX FIFO is less than the 16 byte threshold.
00 Receive FIFO is full.
01 The number of bytes in the Receive FIFO has reached or exceeded 16 bytes
10 Receive FIFO is empty
11 The number of bytes in the Receive FIFO is less than the 16 byte threshold.
Receive FIFO.This is the received data byte read from the RX FIFO. The status bits of
this byte can be read from the status register. The FIFO status is not changed
immediately when a write or read occurs. It is updated after the data has settled and the
transfer to the last available position has finished.
Table 170 - HDLC Status Register(Y1D) (E1)
Table 172 - HDLC Receive FIFO(Y1F) (E1)
Table 171 - HDLC Receive CRC(Y1E) (E1)
Functional Description
Functional Description
Functional Description
Advance Information