MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 34

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Table 149 -Interrupts and I/O Control Register (R/W Address Y02) (E1)............................................................ 172
Table 150 -DL, CCS, CAS and Other Control Register (R/W Address Y03) (E1) ............................................... 173
Table 151 -Signaling Period Interrupt Word (R/W Address Y04) (E1) ................................................................ 173
Table 152 -CAS Control and Data Register (R/W Address Y05) (E1)................................................................. 174
Table 153 - HDLC & CCS ST-BUS Control Register (R/W Address Y06) (E1)................................................... 175
Table 154 -CCS to ST-BUS CSTi and CSTo Map Control Register (R/W Address Y07) (E1)............................ 176
Table 155 -DataLink Control Register (R/W Address Y08) (E1) ......................................................................... 177
Table 156 -Receive Idle Code Register(Y09) (E1) .............................................................................................. 178
Table 157 -Transmit Idle Code Register(Y0A) (E1)............................................................................................. 178
Table 158 -Synchronization & CRC-4 Remote Status (R Address Y10) (E1) ..................................................... 179
Table 159 -CRC-4 Timers & CRC-4 Local Status (R Address Y11) (E1)............................................................ 181
Table 160 -Alarms & Multiframe Signaling (MAS) Status (R Address Y12) (E1) ................................................ 182
Table 161 -Non-Frame Alignment (NFAS) Signal and Frame Alignment Signal (FAS) Status
(R Address Y13) (E1) .......................................................................................................................................... 183
Table 162 -Phase Indicator Status (R Address Y14) (E1)................................................................................... 184
Table 163 -PRBS Error Counter & PRBS CRC-4 Counter (R/W Address Y15) (E1) .......................................... 184
Table 164 -Loss of Basic Frame Synchronization Counter with Auto Clear (R/W Address Y16) (E1) ................ 185
Table 165 -E-bit Error Counter (R/W Address Y17) (E1) .................................................................................... 185
Table 166 -Bipolar Violation (BPV) Error Counter (R/W Address Y18) (E1) ....................................................... 186
Table 167 -CRC-4 Error Counter (R/W Address Y19) (E1)................................................................................. 186
Table 168 -Frame Alignment Signal (FAS) Bit Error Counter & FAS Error Counter (R/W Address Y1A) (E1) ... 187
Table 169 -Transmit Byte Counter Position and HDLC Test Status(Y1C) (E1) .................................................. 187
Table 170 -HDLC Status Register(Y1D) (E1)...................................................................................................... 188
Table 171 -HDLC Receive CRC(Y1E) (E1)......................................................................................................... 188
Table 172 -HDLC Receive FIFO(Y1F) (E1)......................................................................................................... 188
Table 173 -HDLC Status Latch(Y23) (E1) ........................................................................................................... 189
Table 174 -Sync, CRC-4 Remote, Alarms, MAS and Phase Latched Status Register (Address Y24) (E1) ....... 189
Table 175 -Counter Indication and Counter Overflow Latched Status Register (Address Y25) (E1) .................. 191
Table 176 -CAS, National, CRC-4 Local and Timer Latched Status Register (Address Y26) (E1)..................... 192
Table 177 -Performance Persistent Latched Status Register (Address Y27) (E1).............................................. 193
Table 178 -E-Bit Error Count Latch (R Address Y28) (E1).................................................................................. 194
Table 179 -Bipolar Violation (BPV) Error Count Latch (R/W Address Y29) (E1)................................................. 194
Table 180 -CRC-4 Error Count Latch (R/W Address Y2A) (E1).......................................................................... 195
Table 181 -Frame Alignment Signal (FAS) Error Count Latch (R/W Address Y2B) (E1) .................................... 195
Table 183 -Sync, CRC-4 Remote, Alarms, MAS and Phase Interrupt Status Register (Address Y34) (E1) ....... 197
Table 184 -Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1) ................. 198
Table 185 -CAS, National, CRC-4 Local and Timer Interrupt Status Register (Address Y36) (E1) .................... 200
Table 186 -HDLC Interrupt Mask Register (Address Y43) (E1) .......................................................................... 201
Table 187 -Sync (Sync, CRC-4 Remote, Alarms, MAS and Phase) Interrupt Mask Register (Address Y44) (E1) ....
202
Table 188 -Counter (Counter Indication and Counter Overflow) Interrupt Mask Register (Address Y45) (E1)... 203
Table 189 -National (CAS, National, CRC-4 Local and Timers) Interrupt Mask Register (Address Y46) (E1) ... 205
xxxiv
16.2.4 Master Status Registers (Y10 - Y1A) Bit Functions....................................................................... 179
16.2.5
16.2.6 Interrupt Vector and Interrupt Status Registers (Y3X) Bit Functions ............................................. 196
16.2.7 Interrupt Vector Mask and Interrupt Mask Registers (Y4X) Bit Functions ..................................... 201
Latched Status Registers (Y2X) Bit Functions............................................................................. 189
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