MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 5

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Framing Algorithm
Channel Associated Signaling
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ABCD or AB bits can be automatically inserted and extracted
Transmit ABCD or AB bits can be passed via the microport or via the CSTi pin
Receive ABCD or AB bits are accessible via the microport or via the CSTo pin
Unused nibble positions in the CSTi/CSTo bandwidth are tri-stated
An interrupt is provided in the event of changes in any of the signaling bits
Receive signaling bits are frozen if digital loss of signal or loss of multiframe alignment is declared
Synchronizes with D4 or ESF protocols
Supports T1DM synchronization with the D4
pattern and timeslot 24 T1DM Sychronization
bytes
Framing circuit is off-line
Transparent transmit and receive mode
In D4 mode Fs bits can be optionally cross
checked with the Ft bits
The start of the ESF multiframe can be
determined by the following methods:
An automatic reframe is initiated if the
framing bit error density exceeds the
programmed threshold
In transparent mode no reframing is forced by
the device
Software can force a reframe at any time
In ESF mode the CRC-6 bits can be
optionally confirmed before forcing a new
frame alignment
During a reframe the signaling bits are
frozen, and error counting for Ft, Fs, ESF
framing pattern and CRC-6 bits is suspended
If J1 CRC-6 is selected the Fs bits are
included in the CRC-6 calculation
J1-CRC-6 and J1-Yellow Alarm can be
independently selected
Supports Robbed Bit Signaling
Optional forced ones insertion
Signaling bits can be debounced by 6 ms
Robbed bit or clear channel signaling are
selected on a channel by channel basis
Signaling interrupts period can be selected:
1, 4 or 8 msec
Free-run
Software reset
Synchronized to the incoming multiframe
T1/J1 Mode
T1/J1 Mode
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Three distinct and independent E1 framing
algorithms
Transparent receive mode
Transparent transmit mode
Optional automatic interworking between
interfaces with and without CRC-4
processing capabilities is supported
An automatic reframe is forced if 3
consecutive frame alignment patterns or
three consecutive non-frame alignment bits
are received in error
In receive transparent mode no reframing is
forced by the device
Software can force a reframe at any time
Software can force a multiframe reframe at
any time
E-bits can optionally be set to zero or one
until CRC synchronization is achieved
Optional automatic RAI
Supports CAS multiframing
Optional automatic Y-bit to indicate CAS
multiframe alignment
Signaling bits can be debounced by 14 ms
Signaling interupt period can be selected 1,
4 or 8 msec
1. Basic frame alignment
2. Signaling multiframe alignment
3. CRC-4 multiframe alignment
E1 Mode
E1 Mode
MT9072
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