MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 126

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
126
15-8
7 - 0
15-12
Bit
7-0
Bit
11
10
9
8
EXZ7-0 Excessive Zero Counter. This counter is incremented once for detection of 8 or more zeros if
Name
TBP7-0
#
Name
RXclk
Vaddr
TXclk
Vcrc
Table 92 - Transmit Byte Counter Position and HDLC Test Status(Y1C) (T1)
#
not used.
B8ZS is turned on. This counter is incremented once if 16 or more zeros are detected if B8ZS
is turned off. This counter counts groups of 8 or more or 16 or more zeros separated by ones.
not used.
This bit represents the receiver clock generated after the RXEN control bit, but before
zero deletion is considered.
This bit represents the transmit clock generated after the TXEN control bit, but before zero
insertion is considered.
This is the CRC recognition status bit for the receiver. Data is clocked into the register and
then this bit is monitored to see if comparison was successful (bit will be high).
This is the address recognition status bit for the receiver. Data is clocked into the Address
Recognition Register and then this bit is monitored to see if comparison was successful
(bit will be high).
Transmit Byte Counter Position. These 7 bits provide the position of the Transmit HDLC
Byte Counter register (YF6). The counter is decremented as a byte of data is sent through
the Transmit FIFO.
When this register reaches the count of one, the next write to the Tx FIFO will be tagged
as an end of packet byte. The counter decrements at the end of the write to the Tx FIFO.
If the Cycle bit of YF2 is set high, the counter will cycle through the programmed value
continuously.
Table 91 - Excessive Zero Counters(Y1B) (T1)
Functional Description
Functional Description
Advance Information