MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 269

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MT9072

Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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Preliminary Information
AC Electrical Characteristics - PCM30 Transmit Timing
1
2
RXDL
PCM 30
Bit Cells
E2i
RxBF
(Output)
RxDLC - Note 2
(Output)
RxDLC - Note 3
(Output)
RxDL
(Output)
RxDLC - Note 2
(Output)
RxDLC - Note 3
(Output)
Note 1 - RxDLC output applies for every second frame (RxBF) pulse (250us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
Note 4 - PCM Timeslot is with reference to RXDL Output. It is delayed 4 bits from RPOS/
Transmit Output Clock Delay
Transmit Output Delay
Characteristics
Bit
Bit
Sa4 to Sa8 clocked in by External Device
Sa4 to Sa8 clocked in by External Device
Example B - 12 kbit/s clock output
Example B - enable output
Sa4, Sa7 and Sa8 clocked in by External Device
Sa4, Sa7 and Sa8 clocked in by External Device
Example A - 20 kbit/s clock output
Example A - enable output
7
7
Bit
6
Bit
6
Bit
5
Bit
5
Figure 74 - Receive Data Link Pin Functional Timing
Timeslot 31
Bit
4
Bit
4
Bit
3
Bit
3
Bit
2
Bit
2
Sym
Bit
Bit
t
1
1
t
TOD
CD
Bit
Bit
0
0
Bit
Bit
Min
7
7
Bit
6
Bit
6
Bit
5
Bit
5
Typ
Timeslot 0
Bit
Sa4
Bit
4
Bit
Sa5
Bit
3
Max
55
55
Bit
Sa6
Bit
2
Units
Bit
Bit
Sa7
1
ns
ns
Bit
Bit
Sa8
0
150pF load on T2o
150pF load on TPOS and
TNEG
Bit
Bit
7
7
Timeslot 1
Test Conditions
Bit
6
Bit
6
Bit
5
Bit
5
MT9072
Bit
4
Bit
4
269

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