MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 198

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
198
Table 183 - Sync, CRC-4 Remote, Alarms, MAS and Phase Interrupt Status Register (Address Y34)
Table 184 - Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1)
Bit
Bit
15
14
13
12
10
11
3
2
1
0
9
MSYNCI
CSYNCI
BSYNCI
RFAILI
Name
Name
CEOI
FEOI
BEOI
SLOI
FEII
BEII
#
Remote CRC-4 Multiframe Generator/Detector Failure Interrupt. This bit is one when the
corresponding latched status bit (RFAILL, register address Y24) is set, and the corresponding
mask bit is unmasked (RFAILM, register address Y44). This bit is cleared when either this
register, or the latched status register is read.
Receive CRC-4 Synchronization Interrupt. This bit is one when the corresponding latched
status bit (CSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (CSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
Receive Multiframe Alignment Interrupt. This bit is one when the corresponding latched
status bit (MSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (MSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
Receive Basic Frame Alignment Interrupt. This bit is one when the corresponding latched
status bit (BSYNCL, register address Y24) is set, and the corresponding mask bit is
unmasked (BSYNCM, register address Y44). This bit is cleared when either this register, or
the latched status register is read.
not used.
Loss of Sync Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (SLOL, register address Y25) is set, and the corresponding mask bit is unmasked
(SLOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Frame Alignment Signal (FAS) Error Counter Overflow Interrupt. This bit is one when the
corresponding latched status bit (FEOL, register address Y25) is set, and the corresponding
mask bit is unmasked (FEOM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
Frame Alignment Signal (FAS) Error Counter Indication Interrupt. This bit is one when
the corresponding latched status bit (FEIL, register address Y25) is set, and the
corresponding mask bit is unmasked (FEIM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
Frame Alignment Signal (FAS) Bit Error Counter Overflow Interrupt. This bit is one when
the corresponding latched status bit (BEOL, register address Y25) is set, and the
corresponding mask bit is unmasked (BEOM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
Frame Alignment Signal (FAS) Bit Error Counter Indication Interrupt. This bit is one
when the corresponding latched status bit (BEIL, register address Y25) is set, and the
corresponding mask bit is unmasked (BEIM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
CRC-4 Error Counter Overflow Interrupt. This bit is one when the corresponding latched
status bit (CEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(CEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Functional Description
Functional Description
(E1)
Advance Information