MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 170

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
170
Bit
6
5
4 REFRM
3
2
1
0
CRCM
CSYN
MFRF
Name
AUTC
AUTY
TIU1
(1)
(0)
(0)
(0)
(0)
(0)
(0)
Table 147 - Alarm and Framing Control Register Y00 (R/W Address Y00) (E1)
Transmit International Use One. This bit is transmitted on the PCM 30 2048kb/s link in bit
position one of timeslot 0 of all the Non-Frame Alignment Signal (NFAS) frames when CRC-4
operation is disabled (CSYN=1 of register address Y00). The TIU1 bit is reserved for international
use and should normally be kept at one. If CRC-4 operation is enabled (CSYN=0), this bit is
ignored.
CRC-4 Synchronization. The CSYN bit in combination with AUTC determines the enabling or
disabling of the CRC functions for timeslot 0. If one and AUTC (register address Y00) is one the
first bits of time-slot 0 for the transmitter are used as international use bits and are programmed by
the TIU0 and TIU1bits (register address Y00). If AUTC is a zero, the CRC-4 calculated bits are
inserted in the FAS frames as shown in Table 12. Also if AUTC is a one, the CSYN has to be low
for the CRC-4 bits to be inserted in the FAS frames. The transmit transparent bit overides the
function of this bit for the transmitter. On the receiver side, if AUTC is 1 and CSYN is 0 then more
than 914 CRC errors in 1 second will cause a resynchronization and search for a basic frame
synchronization. If AUTC is a 1 and CSYN is 1 than CRC errors are ignored. If AUTC is a zero
than more than 914 CRC errors in 1 second will result in basic frame reframe.
Reframe. A one-to-zero transition of this bit results in the execution of the reframing function (the
search for a new basic frame position). The basic frame alignment pattern is x0011011 in timeslot
0 of alternate frames.
Automatic CRC-interworking. If zero, automatic CRC-interworking is activated. If one, it is
deactivated. See Framing Algorithm section, Table 13 for details.
CRC-4 Modification. If one, the transmit CRC-4 remainder is modified when the device is in
transmit transparent mode (TxTRS=1 of register address Y03) in accordance with the local
datalink. The received CRC-4 remainder from the originating node is modified to reflect only the
changes in the local transmit DataLink. If zero, time-slot 0 data from DSTi will not be modified in
transmit transparent mode. This feature can used for intermediate nodes where 2 end nodes are
commmunicating for framing/signalling and 2 intermediate nodes are sending datalink information
in accordance with appendix C of G.706.
Automatic Y-Bit Operation. This bit determines the source for the Remote Multiframe Alarm
Indication bit (the Y bit) of the transmit PCM30 signal (time-slot 16 bit 6 of every frame 0 of the CAS
multiframe). If zero, the source for the Y bit is the Y bit of the Receive Alignment Signals Status
Register (address Y12), and consequently, will change automatically. That is, Y=0 when multiframe
alignment has been acquired (Y=0 of status register), and Y=1 when multiframe alignment has not
been acquired (Y=1 of status register).
If the AUTY bit is set to one, the Y bit is controlled through the Y bit of the CAS Control and Data
Register (address Y05).
Multiframe Reframe. If one, for at least one frame, and then cleared, the selected framer (Y) will
initiate a search for a new signalling multiframe position. Reframing function is activated on the
one-to-zero transition of the MFRF bit.
The signalling multiframe algorithm will align to the first multiframe alignment signal pattern (MFAS
= 0000) it receives in the most significant nibble of channel 16 (status register address Y10 bit
MSYNC is zero). Signalling multiframing will be lost when two consecutive multiframes are
received in error.
Functional Description
Advance Information