MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 87

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
PRBS type (2
system debugging and testing without additional external hardware.
If control bit ADSEQ (register address Y01) is zero, any transmit (internal DSTi) timeslot or combination of
transmit timeslots may be connected to the PRBS generator. Timeslot n is selected by setting the TTSTn bit in
the Timeslot n Control Register (address Y90-YA7), where n is 0 to 23. Any data sent on DSTi is overwritten on
the selected timeslots before being output to TPOS/TNEG.
Similarly, if control bit ADSEQ is zero, any receive timeslot or combination of receive timeslots may be
connected to the PRBS decoder. Timeslot n is selected by setting the RRSTn bit in the Timeslot n Control
Register (register address Y90-YA7), where n is 0 to 23.
PRBS data is distributed to the transmit channels sequentially one byte at a time. Consequently, the data
received must be in the same order that it was sent, in order for the PRBS decoder to correctly operate on the
data.
If one channel is tested at a time, then the PRBS transmit timeslot does not have to match the PRBS receive
timeslot. However, if more than one channel is tested, then the number of transmit timeslots must match the
number of receive timeslots, and the order of the transmit timeslots must match the order of the receive
timeslots. This will ensure that the sequential data bytes received by the PRBS decoder are in the correct
order. Consequently, particular care must be taken when using an external loopback where the channel order
may be reversed, or where the data has passed through a digital switch which doesn’t buffer all channels to the
same degree.
The PRBS decoder must have sufficient data pass through it before it begins to operate correctly, therefore, the
errors generated by the decoder immediately following start-up should be ignored.
If the PRBS testing is performed in an external loop around using Timeslot Control, then both Timeslot Control
bits TTSTn and RRSTn should also be set.
13.1.5
If the control bit ADSEQ is one (register address Y01), the Mu-law digital milliwatt sequence (Table 45) defined
by G.711, is available to be transmit on any combination of selected channels. The channels are selected by
setting the TTSTn control bit (register address Y90-YA7). The same sequence is available to replace received
data on any combination of DSTo channels. This is accomplished by setting the RRSTn control bit (register
address Y90-YA7) for the corresponding channel. Note that Bit 1 is the sign bit and is sent first.
Register
Address
Y90-YA7
Y01
Y15
Y34
Y44
T1 Mu-law Milliwatt
15
-1). Bits which don’t match are counted by an internal error counter. This provides for powerful
Line Interface and Coding
Per Channel Control
PRBS Error Counter and CRC
Multiframe Counter for PRBS
Receive Sync Interrupt Status
Receive Sync Interrupt Mask
Register
Table 44 - Registers Related to PRBS Testing (T1)
ADSEQ bit chooses between Milliwatt test sequence and
transmitted PRBS test sequence.
If TTST is set for any channel, the test sequence will be
transmitted on that DS1 timeslot. If RRST is set for any channel,
the test sequence will be expected on the receivePCM24 slot.
The PRBS Error Counter contains error count on the received
PRBS sequence.
PRBSOI will indicate an overflow on the PRBS Error Counter.
PRBSOIM is the mask for PRBSOI.
Description
MT9072
87