MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 76

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
In E1 IMA mode the backplane operates at 2.048Mbit/s in a manner similar to the ST-BUS, the timing diagrams
are shown in Figures 51 and 52. The receive slip buffer is bypassed in this mode.
Note that in IMA mode the ST-BUS selection in register 900 is ignored.
If IMA mode is selected the following functions are not supported:
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9.1.4
Dedicated multiframe boundary pins are included which provide the user the option of setting the multiframe
boundaries and identifying the multiframe boundaries with an external device. Refer to the RxMF and TxMF pin
descriptions.
9.1.5
9.1.5.1 Reset Operation (RESET Pin, RST Bit and RSTC Bit)
The MT9072 can be reset using the hardware RESET pin or the software reset bits: RST (register address
YF1) and RSTC (address 900). The RST bit resets a particular framer and the RSTC bit is a global software
reset bit.
On initial power up, a hard reset must be done using the RESET pin. A valid reset condition requires both of
these inputs to be held low for a minimum of 100ns. These inputs should be set to zero during initial power up,
then set to one.
After initial power up, the MT9072 can be reset using the hardware RESET pin or the software reset bit RSTC
(register address 900). When the device emerges from its reset state, it will begin to function in T1 mode and
the control registers will be initialized as described in Table 36. Clearing the T1E0 bit in register 900 to place
the MT9072 in E1 mode will cause another internal reset and the control registers will be initialized to their E1
defaults as described in Table 37. In addition, individual framers may be reset with the software reset bit RST.
Using the RST will reset the individual framer to its default E1 or T1 setting. RST will not affect the common
control register (9xx). All reset operations take 1 full frame (125 us) to complete. Refer to the RESET pin
description, RSTC and RST bit descriptions for additional details.
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Register
Address
8.192 Mbits backplane mode
Robbed bit signaling and CAS
Digital milliwat patterns
One, two second timers and latching of counters at 1 sec timer
GCI mode
Data link insertion extraction of FDL (the HDLC can be assigned to the FDL IMA mode)
Y00
Y06
Control Pins
Signaling Multiframe Boundary (RxMF, TxMF Pins)
Framing Mode Select
HDLC & Datalink Control
Register
Table 35 - Registers Related to IMA Mode
Setting the IMA bit will cause the framer to enter IMA mode.
E1.5CK bit must be set to provide a 1.544 MHz clock on
RXDLC.
Description
Advance Information