MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 75

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
See Figures 22 and 23 for processor timing requirements. See the Registers section for detailed register
descriptions.
The MT9072 includes a status register which contains a15 bit identification code(address 912) for the MT9072.
This code identifies the marketing revision. This byte allows user software to track device revisions, and device
variances and provide system variations if necessary. Refer to the registers section for details.
9.1.1.1 CS and IRQ
The MT9072 includes a CS pin for applications where a single processor is controlling numerous peripherals.
Processor access can be disabled without affecting framer operation. Refer to the CS pin description for details.
An IRQ pin is provided with an extensive suite of maskable interrupts. Refer to the IRQ pin description and the
interrupt section for interrupt processing details.
9.1.2
The ST-BUS is used for data and signaling access only and does not carry any MT9072 control information.
Payload data is accessed through the DSTi and DSTo streams. Channel Associate Signalling bits and
Common Channel Signaling bits can be accessed through CSTi and CSTo streams. See Tables 2 to 6 for ST-
BUS Channel to transmit/receive timeslot mapping.
Dedicated data link pins are included which provide the user the option of bypassing the receive elastic buffer
and accessing data link (DL) data with an external controller. The MT9072 provides numerous additional
methods for accessing the DL, refer to the data link sections for details.
9.1.3
In the IMA (Inverse Mux for ATM) mode the transmit and receive timing on the backplane are independent
unlike the ST-BUS where all of the streams (DSTi/DSTo) are synchronous with a single clock (CKI) and a single
frame pulse (FPI). The IMA mode is specifically intended to interface to the Zarlink IMA devices such as
MT90220.
In IMA mode the RXBF and RXDLC pins provide the receive frame pulse and receive clock for the data
appearing at the DSTo pin. The FPi and CKi pins are inputs for the transmit frame pulse and transmit clock for
data appearing at the DSTi pin.
Note that in the IMA Mode, the slip buffers will be bypassed. On the transmit side data is accepted in the DSTi
streams with respect to the CKi clock. The transmit clock TXCL (an input clock in T1 Mode) has to be
synchronous to the CKi clock. On the receive side the EXCLi clock is the master and the DSTo data is
synchronous to the EXCLi clock.
In T1 IMA mode the backplane operates at 1.544 Mbit/s with the frame pulse centered on the S-Bit, the timing
diagrams are shown in Figures 32 and 33. In order to provide the extracted 1.544 Mbit/s clock the E1.5CK bit in
the Data Link Control Register (Y06) must be set. The receive and transmit slip buffers are bypassed in this
mode.
Selects the framer(s) (i.e. 0, 1, 2,
3,4,5,6,7,all, global)
ST-BUS Interface (DSTi, DSTo, CSTi, CSTo Pins)
IMA Interface (DSTi, DSTo, Pins)
A
11
,A
10
,A
9
,A
8
Table 34 - Framer and Register Access
Selects the register group (i.e.
Control, Status, Interrupt Mask etc.)
A
Address
7
,A
6
,A
5
A
4
Selects the particular register in the
register group (i.e. PRBS Error
Counter etc.)
A
3
,A
2
,A
1
,A
MT9072
0
75