MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 51

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
4.2.2.1 E1 Automatic CRC-4 Interworking
When control bit AUTC (register address Y00) is set to zero, the MT9072 framing algorithm supports automatic
interworking of interfaces with and without CRC-4 processing capabilities. That is, if an interface with CRC-4
capability, achieves valid basic frame alignment, but does not achieve CRC-4 multiframe alignment by the end
of a predefined period, the distant end is considered to be a non-CRC-4 interface. When the distant end is a
non-CRC-4 interface, the near end automatically suspends receive CRC-4 functions, continues to transmit
CRC-4 data to the distant end with its E-bits set to zero, and provides a status indication. Naturally, if the
distant end initially achieves CRC-4 synchronization, CRC-4 processing will be carried out by both ends.
When control bit AUTC is one, Automatic CRC-4 Interworking is deactivated. In this case, if the Automatic
Remote Alarm Indication (RAI) Operation (ARAI) control bit (register address Y00) is low, and if CRC-4
multiframe alignment is not found in 400 msec, then the transmit Remote Alarm Indication (RAI) (bit 3 (A) of the
transmit NFAS) will be continuously high until CRC-4 multiframe alignment is achieved.
The TE control bit (register address Y00) for transmit E bits will have the same function in both states of AUTC.
That is, when CRC-4 synchronization is not achieved the state of the transmit E-bits will be the same as the
state of the TE control bit. When CRC-4 synchronization is achieved the transmit E-bits will function as per ITU-
T G.704 as described in the previous section. Table 13 outlines the operation of the AUTC, ARAI and TALM
control bits of the MT9072.
4.2.3
Refer to the section on Channel Associated Signaling (CAS) Operation.
4.2.4
The MT9072 contains three distinct framing algorithms: basic frame alignment, signaling multiframe alignment
and CRC-4 multiframe alignment. Figure 7 is a state diagram that illustrates these algorithms and how they
interact.
After power-up, the basic frame alignment framer will search for a frame alignment signal (FAS) in the PCM30
receive bit stream. Once the FAS is detected, the corresponding bit 2 of the non-frame alignment signal
AUTC
0
0
0
1
1
1
E1 Channel Associated Signaling (CAS) Multiframing (Timeslot 16)
E1 Framing Algorithm
ARAI
0
1
1
0
1
1
Table 13 - Operation of AUTC, ARAI and TALM Control Bits (E1)
TALM
X
X
0
1
0
1
Automatic CRC-interworking is activated. If no valid CRC MFAS is being
received, transmit RAI will flicker high with every reframe (8msec.), this cycle
will continue for 400 msec., then transmit RAI will be low continuously. The
device will stop searching for CRC MFAS, continue to transmit CRC-4
remainders, stop CRC-4 processing, indicate CRC-to-non-CRC operation and
transmit E-bits to be the same state as the TE control bit (control register
address Y00).
Automatic CRC-interworking is activated. Transmit RAI is low continuously.
Automatic CRC-interworking is activated. Transmit RAI is high
continuously.
Automatic RAI is activated. Automatic CRC-interworking is de-activated. If
no valid CRC MFAS is being received, transmit RAI flickers high with every
reframe (8 msec.), this cycle continues for 400 msec, then transmit RAI
becomes high continuously. The device continues to search for CRC MFAS
and transmit E-bits are the same state as the TE control bit. When CSYN = 0,
the CRC MFAS search is terminated and the transmit RAI goes low.
Automatic RAI is activated. Automatic CRC-interworking is de-activated.
Transmit RAI is low continuously.
Automatic RAI is activated. Automatic CRC-interworking is de-activated.
Transmit RAI is high continuously.
Description
MT9072
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