MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 42

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
2.2 T1 Interface to the Physical Layer Device
Control bits in the Line Interface and Coding word (address Y01) determine the format of the PCM24 transmit
and receive signals. Three physical interface formats are provided including RZ dual rail, NRZ dual rail and
NRZ single rail.
The detailed timing diagrams are presented in Figures 45 to Figures 48.
RZ Dual Rail - On the Transmit side the pulse width is approximately half the duration of the PCM24 bit cell
centered around the falling edge of TXCL. On the receive side RPOS and RNEG are sampled on the falling
edge of EXCLi. Note that the CLKE bit in register Y01(selectable for edge sampling) has no effect in RZ mode.
NRZ Dual Rail - With this format, pulses are present for the full bit cell, which allows the set-up and hold times
to be easily met. For the receiver the sampling point can be the rising edge or the falling edge of the EXCLi
clock, depending on the CLKE bit in Register Y01. The transmitted data can be output either on the rising or
falling edge of TXCL selected by the CLKE bit. TXCL is an input in T1 mode and an output in E1 mode.
NRZ Single Rail - This NRZ format is not dual rail, and therefore, only requires a single output line and a single
input line (i.e., TPOS and RPOS). The CLKE bit in Register Y01 controls the TXCL clock edge and the EXCLi
sampling edge.
2.3
B8ZS (zero code substitution) is selectable globally for both the transmit and receive path (register Y01).
Jammed bit 7, GTE, DDS or BELL zero code suppression are also available for the transmitter and
receiver(register Y01).
Different schemes for provision of ones density can be selected with bits ZCS2:0 (registers Y01). GTE
suppression is achieved by replacing the LSB of zero bytes by a one except for the signaling frame. DDS
suppression is replacement of zero byte by 10011000. Bell code suppression is replacement of bit 1(second bit
after LSB) of a zero byte. Jammed bit seven selection will replace the LSB of each channel with a ’1’.
2.4
Bit 4 of address Y10 (PDV) toggles if the receive data fails to meet ones density requirements. It will toggle
upon detection of 16 consecutive zeros in the line data, or if there are fewer than N ones in a window of 8(N+1)
bits - where N = 1 to 23.
The transmit T1 data is monitored and if the 12.5% density requirement is not met over a maximum 192 bit
window a one is inserted in a non-framing bit. The window and PDV criteria is the same as the received PDV.
3.0
3.1
PCM30 (E1) basic frames are 256 bits long and are transmitted at a frame repetition rate of 8000 Hz, which
results in an aggregate bit rate of 256 bits x 8000/sec = 2.048Mbits/sec. The actual bit rate is 2.048Mbit/s +/-50
ppm encoded in HDB3 (High Density Bipolar 3) format. Basic frames are divided into 32 timeslots numbered 0
to 31, see Figure 6. Each timeslot is 8 bits in length and is transmitted most significant bit first (numbered bit 1).
This results in a single timeslot data rate of 8 bits x 8000/sec. = 64 kbit/s.
It should be noted that the Zarlink ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit
of an eight bit channel is numbered bit 7, see Figure 5. Therefore, ST-BUS bit 7 is synonymous with PCM30 bit
1; bit 6 with bit 2: and so on, see Zarlink Application Note MSAN-126 for more details on the ST-BUS.
42
T1 Line Coding
E1 Interface to the System Backplane
T1 Pulse Density
PCM30 Interface (E1)
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