MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 101

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
15.2 Test Access Port (TAP) Controller
The TAP Controller generates clock and control signals for the Instruction Register (IR) and the Test Data
Registers (TDR’s). The TAP Controller operates synchronously with the TCK input clock and responds to the
TMS input signal to generate control signals which shift, capture, or update data through either the IR or the
TDR’s.
15.3 Instruction Register
The Instruction Register (IR) is a 3-bit register which allows one of four test instructions to be shifted into the
device. Test instructions are serially loaded into the IR from the TDI pin by the TAP Controller. Refer to Table 53
which describes the test instructions provided by the MT9072; these instructions are in accordance with the
IEEE 1149.1 standard.
15.4 JTAG Data Registers
As specified in IEEE 1149.1, the JTAG Interface must contain as a minimum the boundary scan register and
the bypass register. The device identification register although optional, is also included in the MT9072.
15.4.1
This is a 32 bit register as defined in Table 54. Note that the part number revision is not the same as the silicon
revision which is not supplied.
Note 1. The following optional JTAG instructions are not supported, INTEST, RUNBIST and USERCODE.
MSB
0
0
0
1
0
1
0
1
Identification Register
Version
(4 bits)
LSB
0000
A
0
0
1
1
0
Instruction
PRELOAD
SAMPLE/
EXTEST
BYPASS
IDCODE
Name
Table 54 - JTAG MT9072 Identification Register
1001 0000 0111 0010
This instruction isolates the framer logic (on chip logic) from the input and output
pins. The signal states at the output pins are determined by the values
programmed (earlier) in the Boundary Scan Register. This instruction allows
testing of board level interconnects (i.e. open, stuck at, bridge).
This instruction performs two functions. On the rising edge of TCK, the SAMPLE
instruction is performed. With this instruction, the signal states at the input and
output pins are loaded into the Boundary Scan Register. On the falling edge of
TCK, the PRELOAD instruction is performed. With this instruction, the signal
states at the output pins is determined by the values programmed (earlier) in the
Boundary Scan Register.
This instruction forces the value of the 32 bit MT9072 Identification Register into
the Instruction Register’s parallel output latches. This is the default instruction
loaded after a JTAG reset.
This instruction connects the Bypass Register between the TDI and TDO pins.
Part Number
Table 53 - JTAG Instruction Register
(16 bits)
9 0 7 2
9072
0 9 0 7 2 1 4 B
Manufacturer Identity
Functional Description
0001 0100 101
(11 bits)
Zarlink
14B
LSB=1
LSB=1
(1 bit)
MT9072
1
101