MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 30

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Table 44 -Registers Related to PRBS Testing (T1)............................................................................................... 87
Table 45 -Mu Law Digital Milliwatt Pattern (T1)..................................................................................................... 88
Table 46 -Alarm Control and Status Bits (T1)........................................................................................................ 88
Table 47 -Registers Related to Maintenance and Alarms (E1) ............................................................................. 89
Table 48 -A-Law Digital Milliwatt Pattern (E1) ....................................................................................................... 91
Table 49 -Alarms and Timers Status Registers (E1) ............................................................................................. 92
14.0 Interrupts........................................................................................................................ 92
Figure 9 -Interrupt Status Registers ...................................................................................................................... 93
Table 50 -Interrupt Vector and Interrupt Source Summary (T1)............................................................................ 95
Table 51 -Interrupt Vector and Interrupt Source Summary (E1)............................................................................ 96
Table 52 -Interrupt Source & Status Register Summary (E1) ............................................................................... 98
15.0 JTAG (Joint Test Action Group) Operation ................................................................. 99
Figure 10 -Boundary Scan Test Circuit Block Diagram ....................................................................................... 100
Table 53 -JTAG Instruction Register ................................................................................................................... 101
xxx
13.2 E1 Maintenance and Alarms .................................................................................................................. 89
14.1 Interrupt Status Register Overview ........................................................................................................ 93
14.2 Interrupt Servicing Methods ................................................................................................................... 94
14.3 T1 Interrupt Vector and Interrupt Source Summary ............................................................................... 95
14.4 E1 Interrupt Vector and Interrupt Source Summary ............................................................................... 96
14.5 E1 Interrupt Source and Interrupt Status Register Summary................................................................. 98
15.1 Test Access Port (TAP)........................................................................................................................ 100
15.2 Test Access Port (TAP) Controller ....................................................................................................... 101
15.3 Instruction Register .............................................................................................................................. 101
13.1.3 T1 Per Timeslot Looping ................................................................................................................. 86
13.1.4 T1 Pseudo-Random Bit Sequence (PRBS) Testing ........................................................................ 86
13.1.5 T1 Mu-law Milliwatt .......................................................................................................................... 87
13.1.6 T1 Alarms ........................................................................................................................................ 88
13.1.7 T1 Per Timeslot Trunk Conditioning ................................................................................................ 89
13.2.1 E1 Error Insertion ............................................................................................................................ 90
13.2.2 E1 Per Timeslot Control .................................................................................................................. 90
13.2.3 E1 Per Timeslot Looping ................................................................................................................. 90
13.2.4 E1 Pseudo-Random Bit Sequence (PRBS) Testing........................................................................ 90
13.2.5 E1 A-law Milliwatt ............................................................................................................................ 91
13.2.6 E1 Alarms ........................................................................................................................................ 91
13.2.7 E1 Automatic Alarms ....................................................................................................................... 92
14.1.1 Interrupt Related Control Bits and Pins ........................................................................................... 94
14.2.1 Polling Method................................................................................................................................. 94
14.2.2 Vector Method ................................................................................................................................. 94
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