MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 27

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Table 8 -D4 Superframe Structure (T1)................................................................................................................. 46
Table 9 -ESF Superframe Structure (T1) .............................................................................................................. 46
Table 10 -G.802 ST-BUS to PCM24 Mapping (T1) ............................................................................................... 47
Table 11 -Registers Related to Framing for MT9072 (E1) .................................................................................... 48
Table 12 -CRC-4 FAS and NFAS Structure (E1) .................................................................................................. 50
Table 13 -Operation of AUTC, ARAI and TALM Control Bits (E1) ........................................................................ 51
Figure 7 -Synchronization State Diagram (E1)...................................................................................................... 53
5.0
Figure 8 -Read and Write Pointers in the Slip Buffers........................................................................................... 54
Table 14 - Registers Related to the Elastic Buffer (T1) ......................................................................................... 55
Table 15 -Registers Related to Elastic Store (E1)................................................................................................. 55
6.0
Table 16 -Registers Related to the Data Link and Bit Oriented Messages (T1).................................................... 56
Table 17 - Data Link and Sa bits Configuration and Status Registers (E1)........................................................... 58
Table 18 -MT9072 National Bit Buffers (E1).......................................................................................................... 59
Table 19 -Transmit PCM30 National Bits from ST-BUS 2.048Mbit/s or 8.192Mbit/s DSTi (E1)............................ 60
4.2
5.1
6.1
6.2
4.1.2
4.1.3
4.1.4
4.2.1
4.2.2
4.2.3
4.2.4
6.1.1
6.2.1
6.2.2
6.2.3
6.2.4
Elastic Buffer ................................................................................................................. 53
Data Link......................................................................................................................... 56
4.2.2.1.............................................................................................. E1 Automatic CRC-4 Interworking 51
4.2.4.1...................................................................Notes for Synchronization State Diagram (Figure 7) 52
6.1.1.1.................................................................... T1 Data Link (DL) Pin Data Received from PCM24 57
6.1.1.2................................................................................ T1 Data Link (DL) Pin Data Sent to PCM24 57
6.2.1.1................................................................... E1 Data Link (DL) Pin Data Transmitted on PCM30 58
6.2.1.2................................. E1 Data Link (DL) Pin Data Received on PCM30 - With No Elastic Buffer 58
6.2.1.3...................................... E1 Data Link (DL) Pin Data Received on PCM30 - With Elastic Buffer 59
E1 Framing............................................................................................................................................. 48
Transmit Elastic Buffer ........................................................................................................................... 55
T1 Data Link ........................................................................................................................................... 56
E1 Data Link (DL) Operation .................................................................................................................. 57
T1 ESF Framing .............................................................................................................................. 46
T1 T1DM Framing ........................................................................................................................... 47
T1 G.802 Mode................................................................................................................................ 47
E1 Basic Framing (Timeslot 0) ........................................................................................................ 49
E1 CRC-4 Multiframing (Timeslot 0)................................................................................................ 49
E1 Channel Associated Signaling (CAS) Multiframing (Timeslot 16) .............................................. 51
E1 Framing Algorithm...................................................................................................................... 51
T1 Data Link (DL) Pin Access ......................................................................................................... 57
E1 Data Link (DL) Pin Access ......................................................................................................... 58
E1 Data Link (DL) National Bit Buffer Access ................................................................................. 59
E1 Data Link (DL) ST-BUS Access ................................................................................................. 59
E1 Timeslot 0 CRC-4 NFAS Receive from PCM30 to DSTo........................................................... 60
Table of Contents (continued)
MT9072
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