MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 91

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
The number of transmit timeslots must match the number of receive timeslots, and the order of the transmit
timeslots must match the order of the receive timeslots. This will ensure that the sequential data bytes received
by the PRBS decoder are in the correct order. Consequently, particular care must be taken when using an
external loopback where the channel order may be reversed, or where the data has passed through a digital
switch which doesn’t buffer all channels to the same degree.
The PRBS decoder must have sufficient data pass through it before it begins to operate correctly, therefore, the
errors generated by the decoder immediately following start-up should be ignored.
If the PRBS testing is performed in an external loop around using Timeslot Control, then both Timeslot Control
bits TTSTn and RRSTn should also be set.
13.2.5
If the control bit ADSEQ is one (register address Y01), the A-law digital milliwatt sequence (Table 48), defined
by G.711, is available to be transmit on any combination of selected channels. The channels are selected by
setting the TTSTn control bit (register address Y90-YAF). The same sequence is available to replace received
data on any combination of DSTo channels. This is accomplished by setting the RRSTn control bit (register
address Y90-YAF) for the corresponding channel. Note that bit 1 is the sign bit and is sent first.
13.2.6
The alarms shown in Table 49 are detected by the receiver. The status register bits provide real time status of the
alarm, while the latched status registers provide a latched status indication, and the interrupt status registers
provide a latched status indication (if unmasked) which generate a maskable interrupt and which are cleared when
read. The persistent status registers provide latched status indication which is only cleared when read while the
real time status bit is not set. See the register bit descriptions for additional details.
Hex
B4
A1
A1
B4
34
21
21
34
E1 A-law Milliwatt
E1 Alarms
Bit 1
0
0
0
0
1
1
1
1
Bit 2
0
0
0
0
0
0
0
0
Table 48 - A-Law Digital Milliwatt Pattern (E1)
Bit 3
1
1
1
1
1
1
1
1
PCM30 Payload Data
Bit 4
1
0
0
1
1
0
0
1
Bit 5
0
0
0
0
0
0
0
0
Bit 6
1
0
0
1
1
0
0
1
Bit 7
0
0
0
0
0
0
0
0
MT9072
Bit 8
0
1
1
0
0
1
1
0
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