MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 171

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
15-14
Bit
13
12
10
11
9
8
7
6
5
4
3
2
1
0
ADSEQ
CRCE
Name
PERR
DLBK
RLBK
NFSE
LOSE
SLBK
PLBK
FASE
L32Z
BVE
(0)
(0)
(0)
(0)
(0)
(0)
E1
(0)
E2
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 148 - Test, Error and Loopback Control Register (R/W Address Y01) (E1)
#
not used.
Digital Loss of Signal Selection. If one, the threshold for digital loss of signal is 32
successive zeros. If zero, the threshold is set to 192 successive zeros.
Digital Milliwatt or Digital Test Sequence. If one, the A-law digital milliwatt analog test
sequence will be selected by the Per Timeslot Control bits TTSTn and RTSTn (register
address Y90 to YAF). If zero, the PRBS 2
the Per Timeslot Control bits TTSTn and RTSTn. The PRBS generator is reset whenever this
bit is set to 1.
Digital Loopback. If one, all timeslots of DSTi are connected to DSTo on the PCM30 side of
the selected framer (Y). If zero, this feature is disabled. See Loopbacks section.
Remote Loopback. If one, all timeslots received on RPOS/RNEG are connected to TPOS/
TNEG on the PCM30 side of the selected framer (Y). If zero, this feature is disabled. See
Loopbacks section.
ST-BUS Loopback. If one, all timeslots of DSTi are connected to DSTo on the ST-BUS side
of the selected framer (Y). If zero, this feature is disabled. See Loopbacks section.
Payload Loopback. If one, all timeslots received on RPOS/RNEG are connected to TPOS/
TNEG on the ST-BUS side(DSTo to DSTi) of the selected framer (Y) (this excludes time-slot
0). Hence the data passes through the receiver and output to DSTo. This DSTo data is looped
back to DSTi which is transmitted to TPOS/TNEG by the transmitter.
If zero, this feature is disabled. See Loopbacks section.
E1 Error Insertion. A zero-to-one transition of this bit inserts a single E1 error into the
transmit PCM30 data (bit position 1 of frame 13 of the CRC-4 Multiframe). A one, zero or one-
to-zero transition has no function.
E2 Error Insertion. A zero-to-one transition of this bit inserts a single E2 error into the
transmit PCM30 data (bit position 1 of frame 15 of the CRC-4 Multiframe). A one, zero or one-
to-zero transition has no function.
Bipolar Violation Error Insertion. A zero-to-one transition of this bit inserts a single bipolar
violation error into the transmit PCM30 data. A one, zero or one-to-zero transition has no
function.
CRC-4 Error Insertion. A zero-to-one transition of this bit inserts a single CRC-4 error into
the transmit PCM30 data. A one, zero or one-to-zero transition has no function.
Frame Alignment Signal Error Insertion. A zero-to-one transition of this bit inserts a single
error into the timeslot zero frame alignment signal of the transmit PCM30 data. A one, zero or
one-to-zero transition has no function.
Non-frame Alignment Signal Error Insertion. A zero-to-one transition of this bit inserts a
single error into bit two of the timeslot zero non-frame alignment signal of the transmit PCM30
data. A one, zero or one-to-zero transition has no function.
Loss of Signal Error Insertion. If one, the selected framer (Y) transmits an all zeros signal
(no pulses) in every PCM30 timeslot, and, the HDB3 control bit (reg address Y02) has no
effect. If zero, data is transmitted normally.
Payload Error Insertion. A zero-to-one transition of this bit inserts a single error in the
transmit payload. A one, zero or one-to-zero transition has no function.
Functional Description
15
-1 bit error rate test sequence will be selected by
MT9072
171