MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 86

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
13.0 Maintenance and Alarms
13.1 T1 Maintenance and Alarms
13.1.1
Six types of error conditions can be inserted into the transmit DS1 data stream through control bits, which are
located in address Y03 -Transmit Error Control Word. These error events include bipolar violation errors
(BPVE), CRC-6 errors (CRCE), Ft errors (FTE), Fs errors (FSE), payload errors (PERR) and a loss of signal
condition (LOSE). If LOSE is one the selected framer transmits an all zeros signal (no pulses) and zero code
suppression is overridden. If LOSE bit is zero, data is transmitted normally.
13.1.2
There are 24 per timeslot control registers occupying a total of 24 unique addresses (Y90-YA7). Each register
controls a transmit timeslot and the equivalent channel data on DSTo. For example, register address Y90 of the
first per timeslot control register contains program control for transmit timeslot 0 and DSTo channel 0.
13.1.3
Any channel or combination of channels may be looped from transmit (sourced from DSTi) to receive (output
on DSTo) ST-BUS channels. When bit 4 (LTSL) in the Per Timeslot Control Word(Y90-YA7) is set the data from
the equivalent transmit channel is looped back onto the equivalent receive timeslot.
Any channel or combination of channels may be looped from receive (sourced from the line data) to transmit
(output onto the line) channels. When bit 5 (RTSL) in the Per Timeslot Control Word is set the data from the
equivalent receive timeslot is looped back onto the equivalent transmit timeslot.
13.1.4
The MT9072 includes both a pseudo random bit sequence (PRBS) generator of type (2
PRBS generator (decoder), which operates on a bit sequence, and determines if it matches the transmitted
86
PRBS Error Counter PEC7-0
PRBS CRC-4 MF
Counter
Loss of Sync
Counter
E-bit Error Counter
BPV Error Counter
CRC-4 Error
Counter
FAS Bit Error
Counter
FAS Error Counter
Description
T1 Error Insertion
T1 Per Timeslot Control
T1 Per Timeslot Looping
T1 Pseudo-Random Bit Sequence (PRBS) Testing
Counter
EEC15-0
VEC15-0
CEC15-0
PCC7-0
BEC7-0
SLC7-0
FEC7-0
Bits
Table 43 - Error Counter and Event Dependency (E1)
Address
Y1A
Y1A
Y15
Y15
Y16
Y17
Y18
Y19
BSYNC
Source Interrupt Status Bits
CRCS1
CRCS2
CALN
REB1
REB2
Bit
Indication Overflow Description
BSYNC
PEI
EEI
VEI
CEI
BEI
FEI
NA
PEO
PCO
EEO
VEO
CEO
BEO
SLO
FEO
NA
NA
NA
E-bit Error
Count Latch
BPV Error
Count Latch
CRC-4 Error
Count Latch
FAS Bit Error
Count Latch
FAS Error
Count Latch
Advance Information
1 Second Latch
15
EEL15-0
VEL15-0
CEL15-0
BEL7-0
FEL7-0
-1), and a reverse
NA
NA
NA
Bit
Address
Y2A
Y2B
Y2B
Y28
Y29
NA
NA
NA