MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 67

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
detailed bit mapping of CSTi timeslots to transmit PCM30 frames. Table 28 shows the detailed bit mapping of
DSTi timeslots to transmit PCM30 frames.
7.2.4
The CSIG control bit (register address Y03) must be set to one for Common Channel signaling (CCS)
operation. CCS on the receive PCM30 link (bit positions one to eight of timeslots 15, 16 and/or 31 of every
frame) is sourced to the ST-BUS DSTo stream and may also be sourced to the ST-BUS CSTo stream. If the
TS15E, TS16E & TS31E control bits (register address Y06) are zero, the receive data will be sourced to the
ST-BUS DSTo stream only, timeslots 15, 16 and 31. If these bits are one, then the signaling data will be
sourced to both the DSTo stream and the ST-BUS CSTo stream. Note that any combination of the TS15E,
TS16E & TS31E control bits (register address Y06) may be enabled. The CSTo destination timeslots for the
receive PCM30 timeslots 15, 16 and 31, are determined respectively by the 15C4-15C0, 16C4-31C0 and
31C4-31C0 (register address Y07) programming bits. Table 29 shows the detailed bit mapping of CSTo
timeslots from receive PCM30 frames. Table 30 shows the detailed bit mapping of DSTo timeslots from receive
PCM30 frames.
Note 1. For 2.048Mbit/s operation, m=1 and n=0.
Note 2. For 8.192Mbit/s operation, m=4 and n =0,1,2,3 where n corresponds to the framer number (i.e. n=0=framer 0... n=3= framer
3)
Note 3. For these functions to be valid, CCS mode must be selected (CSIG=1 register address Y03), and CSTi ST-BUS mode must
be selected (TS15E=1, TS16E=1 & TS31E=1 register address Y06), and the preferred source CSTi timeslot should be selected
(15C4-0, 16C4-0 & 31C4-0 register address Y07).
Note 1. For 2.048Mbit/s operation, m=1 and n=0.
Note 2. For 8.192Mbit/s operation, m=4 and n =0,1,2,3 where n corresponds to the framer number (i.e. n=0=framer 0... n=3= framer 3).
Note 3. For these functions to be valid, CCS mode must be selected (CSIG=1 register address Y03), and DSTi ST-BUS mode must be selected
(TS15E=0, TS16E=0 & TS31E=0 register address Y06).
CRC-4
Frame
CRC-4
Frame
all
all
all
all
all
all
E1 Common Channel Signaling (CCS) Receive from PCM30 to CSTo and DSTo
Table 27 - Transmit PCM30 CCS from ST-BUS 2.048Mbit/s or 8.192Mbit/s CSTi (E1)
Table 28 - Transmit PCM30 CCS from ST-BUS 2.048Mbit/s or 8.192Mbit/s DSTi (E1)
n + m(15)
n + m(16)
n + m(31)
Timeslot
n + m(0 to 31)
n + m(0 to 31)
n + m(0 to 31)
Any one of 32
Any one of 32
Any one of 32
Timeslot
ST-BUS DSTi
ST-BUS CSTi
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
Data Bits (B7-B0)
Data Bits (B7-B0)
Timeslot
15
16
31
Timeslot
15
16
31
CRC-4
Frame
CRC-4
Frame
all
all
all
all
all
all
PCM30 Transmit
PCM30 Transmit
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
P1, P2, P3, P4, P5, P6, P7, P8
Data Bits (B1-B8)
Data Bits (B1-B8)
MT9072
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