MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 54

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Advance Information
In a multi-trunk slave or loop-timed system (i.e., PABX application) a single trunk will be chosen as a network
synchronizer, which will function as described in the previous paragraph. The remaining trunks will use the
system timing derived from the synchronizer to clock data out of their slip buffers. Even though the signals from
the network are synchronous to each other, due to multiplexing, transmission impairments and route diversity,
these signals may jitter or wander with respect to the synchronizing trunk signal. Therefore, the EXCLi clocks
of non-synchronizer trunks may wander with respect to the EXCLi clock of the synchronizer and the system
bus.
Network standards state that, within limits, trunk interfaces must be able to receive error-free data in the
presence of jitter and wander (refer to network requirements for jitter and wander tolerance). The MT9072 will
allow a maximum of 26 channels (208 UI, unit intervals) of wander and low frequency jitter before a frame slip
will occur.
The minimum delay through the receive slip buffer is approximately two channels and the maximum delay is
approximately 60 channels (see Figure 8).
When the CKi and the EXCLi clocks are not phase-locked, the rate at which data is being written into the slip
buffer from the line side may differ from the rate at which it is being read out onto the ST-BUS. If this situation
persists, the delay limits stated in the previous paragraph will be violated and the slip buffer will perform a
controlled frame slip. That is, the buffer pointers will be automatically adjusted so that a full frame is either
repeated or lost. All frame slips occur on frame boundaries.
Two status bits, RSLP and RSLPD (register address Y10 for E1 and Y13 for T1), give indication of a slip
occurrence and direction. RSLP changes state in the event of a slip. If RSLPD=0, the slip buffer has overflowed
and a frame was lost; if RSLPD=1, a underflow condition occurred and a frame was repeated. A maskable
interrupt status bit RSLIPI (register address Y34 for E1 and Y36 for T1) is also provided.
Figure 8 illustrates the relationship between the read and write pointers of the receive slip buffer. Measuring
clockwise from the write pointer, if the read pointer comes within two channels of the write pointer a frame slip
will occur, which will put the read pointer 34 channels from the write pointer. Conversely, if the read pointer
moves more than 60 channels from the write pointer, a slip will occur, which will put the read pointer 28
channels from the write pointer. This provides a worst case hysteresis of 13 channels peak (26 channels peak-
to-peak) or a wander tolerance of 208 UI. The registers relevant to controlling and observing the elastic buffer
in T1 mode are shown in Table 14. The registers related to elastic buffer for E1 are shown in Table 15.
Write Pointer
Read Pointer
Read Pointer
60 CH
13 CH
2 CH
Wander Tolerance
512 Bit
15 CH
47 CH
Elastic
Store
-13 CH
34 CH
28 CH
Read Pointer
Read Pointer
Figure 8 - Read and Write Pointers in the Slip Buffers
In T1 mode, the transmit and receive elastic buffers also serve the purpose of rate conversion between the
1.544 Mbit/s line rate and the 2.048 Mbit/s backplane rate. Consequently, in T1 mode the elastic buffers
cannot be bypassed, except for the special case of T1 IMA mode.
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