MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 84

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
12.0 Performance Monitoring
12.1 T1 Error Counters
The MT9072 has nine error counters for each framer, which can be used for maintenance testing and ongoing
measurement of the quality of a DS1 link and to assist the designer in meeting specifications such as TR62411
and T1.403. All counters can be preset or cleared by writing to the appropriate counter registers.
Associated with each counter is a maskable event occurrence interrupt and a maskable counter overflow
interrupt. Overflow interrupts are useful when cumulative error counts are being recorded. For example, every
time the framing bit error counter overflow interrupt (FEO) occurs, 65536 frame errors have been received
since the last FEO interrupt. Also if a counter overflows, the overflow indicators are latched in the Overflow
reporting latch register(Y24).
All counters are cleared by a counter clear bit -CNTCLR - low to high transition (bit 2 of the IO Control Word,
YF1). An alternative approach to event reporting is to mask error events and to enable the 1 second sample bit
(SAMPLE - bit 1 of the Interrupt and IO Control Word). When this bit is set the latched version of the
counters(Y28 to Y2C) for change of frame alignment, loss of frame alignment, bpv errors, crc errors, errored
framing bits, and multiframes out of sync are updated on one second intervals coincident with the maskable
one second interrupt timer.
12.2 E1 Error Counters
The MT9072 has eight error counters, which can be used for maintenance testing, and ongoing measurement
of the quality of a PCM30 link and to assist the designer in meeting specifications such as ITU-T I.431 and
G.821. All counters can be preset or cleared by writing to the appropriate locations. In addition, four error count
latches are provided which latch the counter data coincident with the one second status bit. Counters can
automatically be cleared (ACCLR register address Y03) after their data is latched. Associated with each
counter is a maskable event indication interrupt and a maskable counter overflow interrupt. Overflow interrupts
84
PRBS Error Counter
and CRC Multiframe
counter for PRBS
Multiframe Out of
Frame Counter
Framing Bit Error
Counter
BPV Counter
CRC-6 Error counter
Out of frame counter,
change of frame
alignment counter
Excessive Zero
counter
Description
Counter
COFA7-0
BPV15-0
OOF7-0,
PSM7-0
MFOOF
EXZ7-0,
CC15-0
FC15-0
PS7-0,
Bits
7-0
Table 41 - Error Counters Summary (T1)
Address Indication
Y1A
Y1B
Y15
Y16
Y17
Y18
Y19
MFOOFI
Interrupt Status Bits
OOFOI
PRBSI
COFAI
CRCI
FBEI
BPVI
EXZI
PRBSMFOI
MFOOFOI Multiframe Out of
Overflow
PRBSOI
COFOIL
OOFOI
EXZOL
CRCOI
BPVOI
FEOI
NA
Frame Count Latch
Framing Bit Error
Counter Latch
Bipolar Violation
Count Latch
CRC-6 Error Count
Latch
Out of Frame, Change
of Frame Alignment
Count Latch
NA
Description
1 Second Latch
Advance Information
FCL15-
COFAL
FL15-0
MFOO
CRCL
OOFL
BPVL
15-0
15-0
NA
7-0
7-0
NA
Bit
0
Address
Y2C
Y2A
Y2B
Y28
Y29
NA
NA
.