MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 192

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
192
Bit Name
0
Table 175 - Counter Indication and Counter Overflow Latched Status Register (Address Y25) (E1)
Bit
15
14
13
12
10
11
9
8
7
6
5
4
3
Table 176 - CAS, National, CRC-4 Local and Timer Latched Status Register (Address Y26) (E1)
PEIL
Sa6V3L
Sa6V2L
Sa6V1L
Sa6V0L
Sa6N8L
CASRL
CALNL
Sa6NL
Sa5VL
Sa5TL
Name
SaNL
SaTL
#
PRBS Error Counter Indication Latch. When the PRBS Error Counter (PEC7-PEC0 register
address Y15 upper byte) is incremented by one, this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y35) is read.
not used.
Sa5 Bit Value Latch. This is the latched value of the Sa5 National bit when the Sa6N8L bit
toggles to one. The Sa5VL bit is cleared when either this register, or the corresponding
interrupt status register (register address Y36) is read.
Sa6 Nibble (bit 3 to 0) Value Latch. This is the latched value of the Sa6 National bits nibble
(bits 3 to 0) when the Sa6N8L bit toggles to one. These bits are cleared when either this
register, or the corresponding interrupt status register (register address Y36) is read.
Sa6 Nibble Eight Consecutive Times Status Latch. When eight consecutive identical
receive Sa6 National bit nibble patterns are received (per sub-multiframe), this status bit is
latched to one. This bit is set on a CRC-4 sub-multiframe basis. This bit is cleared when either
this register, or the corresponding interrupt status register (register address Y36) is read.
Sa6 Nibble Change Status Latch. When a received Sa6 National bit nibble (per sub-
multiframe) changes value, this status bit is latched to one. This bit is set on a CRC-4 sub-
multiframe basis. This bit is cleared when either this register, or the corresponding interrupt
status register (register address Y36) is read.
Sa Nibble Change Status Latch. When any receive National (i.e. Sa5,Sa6,Sa7 or Sa8) bits
nibbles changes value, this status bit is latched to one. This bit is set on a CRC-4 sub-
multiframe basis. This bit is cleared when either this register, or the corresponding interrupt
status register (register address Y36) is read.
Sa5 Bit Change Status Latch. When a received Sa5 National bit changes value, this status
bit is latched to one. This bit is set on a CRC-4 NFAS frame basis. This bit is cleared when
either this register, or the corresponding interrupt status register (register address Y36) is
read.
Sa Bit Change Status Latch. When any receive National (i.e. Sa5,Sa6,Sa7 or Sa8) bit
changes value, this status bit is latched to one. This bit is set on a CRC-4 NFAS frame basis.
This bit is cleared when either this register, or the corresponding interrupt status register
(register address Y36) is read.
Receive Channel Associated Signaling (CAS) Change Latch. When any of the receive
CAS (i.e. ABCD) bits in the Receive CAS Data Registers (address Y70-Y8F) change state,
this status bit is latched to one. This bit is set on a basic frame (FPi) basis. This bit is cleared
when either this register, or the corresponding interrupt status register (register address Y34)
is read.
CRC-4 Alignment 2ms Timer Latch. When the CALN status bit (register address Y11)
toggles from zero to one, this status bit is latched to one. This bit is set on a 2ms or CRC-4
multiframe frame basis. This bit is cleared when either this register, or the corresponding
interrupt status register (register address Y36) is read.
Functional Description
Functional Description
Advance Information