MT90823AG Zarlink Semiconductor, Inc., MT90823AG Datasheet
MT90823AG
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MT90823AG Summary of contents
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... ALE RD /WR Figure 1 - Functional Block Diagram MT90823 3V Large Digital Switch ISSUE 4 Ordering Information MT90823AP 84 Pin PLCC MT90823AL 100 Pin MQFP MT90823AB 100 Pin LQFP MT90823AG 120 Pin PBGA -40 to +85 ° C Large Digital Switch RESET ODE STo0 STo1 STo2 Parallel STo3 STo4 ...
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MT90823 CMOS STi0 STi1 13 STi2 STi3 15 STi4 STi5 17 STi6 STi7 19 STi8 STi9 21 STi10 STi11 23 STi12 STi13 25 STi14 STi15 27 F0i FE/HCLK 29 VSS CLK 31 VDD STi0 STi1 82 STi2 ...
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A VSS VSS STo14 STo12 STo10 STo9 B VSS VSS STo15 STo13 STo11 STo8 C STi0 STi1 VSS VDD VSS VDD D STi2 STi3 VDD E STi4 STi5 VSS F STi6 STi7 VDD ...
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MT90823 CMOS Pin Description Pin # 84 100 100 120 PLCC MQFP LQFP BGA 1, 11, 31, 41, 28, A1,A2,A12,A13, 30, 54 56, 66, 38, B1,B2,B7,B12, 64, 75 76, 99 53, B13,C3,C5,C7, 63, C9,C11,E3,E11 73, G3,G11,J3,J11, 96 L3,L5,L7,L9,L11, M2,M12,M13,N1 2, ...
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Pin Description (continued) Pin # 84 100 100 120 PLCC MQFP LQFP BGA 14- N6,M7,N7,N8, 48 ...
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MT90823 CMOS Pin Description (continued) Pin # 84 100 100 120 PLCC MQFP LQFP BGA N12 M11 N13 55 - 32- L12,L13,K12 K13,J12,J13, H12,H13 65 - 42-49 ...
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Pin Description (continued) Pin # 84 100 100 120 PLCC MQFP LQFP BGA - 30 ...
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MT90823 CMOS streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at ...
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CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels. 8.192 Mb/s Serial Links (DR0=0, DR1=1) When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams ...
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MT90823 CMOS Delay Through the MT90823 The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities ...
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AS/ALE to identify the appropriate bus timing connected to the MT90823. If DS/RD is high at the falling edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is low ...
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MT90823 CMOS of the connection memory is transferred to the ST-BUS outputs. If the MC bit is low, the contents of the connection memory stream address bit (SAB) and channel address bit (CAB) defines the source information (stream and channel) ...
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If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero. Initialization of the MT90823 During power up, the TRST pin should ...
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MT90823 CMOS Read/Write Address: Reset Value Bit Name 15-10 Unused Must be zero for normal operation. 9-5 BPD4-0 Block Programming Data. These bits carry the value to be loaded into ...
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Read Address: 02 Reset Value: 0000 CFE FD11 0 Bit Name Unused Must be zero for normal operation. 12 CFE Complete Frame Evaluation. When CFE = 1, the frame evaluation ...
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MT90823 CMOS Read/Write Address Reset value: 0000 OF32 OF31 OF30 DLE3 OF22 OF72 OF71 OF70 DLE7 OF62 OF112 OF111 OF110 DLE11 ...
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Input Stream Offset No clock period shift (Default) + 0.5 clock period shift +1.0 clock period shift +1.5 clock period shift +2.0 clock period shift +2.5 clock period shift +3.0 clock period shift +3.5 clock period shift +4.0 clock period ...
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MT90823 CMOS V/C MC CSTo OE LPBK Bit Name 15 LPBK 14 V CSTo SAB3-0 7 (Note CAB6-0 (Note 1) Note 1: If ...
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JTAG Support The MT90823 JTAG interface conforms to the IEEE 1149.1 Boundary-Scan standard Boundary-Scan Test (BST) design-for-testability technique it specifies. The operation boundary-scan circuitry is controlled by an external test access port (TAP) Controller. Test Access Port (TAP) The Test ...
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MT90823 CMOS Boundary Scan Bit 0 to Bit 117 Device Pin Output Tristate Scan Control Cell STo7 0 1 STo6 2 3 STo5 4 5 STo4 6 7 STo3 8 9 STo2 10 11 STo1 12 13 STo0 14 15 ...
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Applications Switch Matrix Architectures The MT90823 is an ideal device for medium to large size switch matrices where voice and grouped data channels are transported within the same frame. In such applications, the voice samples have to be time interchanged ...
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MT90823 CMOS Wide Frame Pulse (WFP) Frame Alignment Mode When the device is in the wide frame pulse mode and if the input data streams are sampled at 3/4 bit time, the device can operate in the HMVIP and MVIP-90 ...
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Streams Switch Matrix (Figure Streams 4,096 x 4,096 Switch Matrix (Figure 6) Figure 9 - 8,192 x 8,192 Channel Switch Matrix DSTo E1 E1/T1 Trunk 0 DSTi 0 DSTo E1 E1/T1 Trunk 1 ...
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MT90823 CMOS Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any 3.3V Tolerant pin I/O (other than supply pins) 3 Voltage on any 5V Tolerant pin I/O (other than supply pins) 4 Continuous Current at digital outputs 5 ...
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AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Frame pulse width (ST-BUS, GCI) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 2 Frame Pulse Setup time before CLK falling (ST-BUS or ...
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MT90823 CMOS AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic 1 Sti Set-up Time 2 Sti Hold Time 3 Sto Delay - Active to Active 4 STo delay - Active to High-Z 5 Sto delay - ...
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F0i t FPS CLK STo Bit 7, Last Ch (Note1) STi Bit 7, Last Ch (Note1) Note 1: 2Mb/s mode, last channel = ch 31, 4Mb/s mode, last channel = ch 63, 8Mb/s mode, last channel = ch 127 Figure ...
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MT90823 CMOS CLK (ST-BUS or) (WFPS mode) CLK (GCI mode HiZ Valid Data STo t ZD Valid Data HiZ STo t XCD CSTo Figure 14 - Serial Output and External Control ODE V CT STo ...
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AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1) Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup from DTA Low on Read ...
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MT90823 CMOS AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2) Characteristics 1 AS pulse width 2 Address setup from AS falling 3 Address hold from AS falling 4 Data setup from DTA Low on Read 5 CS hold after ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 ...
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Pin #1 Corner 3.00*45 (4x) 20.00 REF 30 Typ. C Seating Plane Package Outlines ...
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Package Outlines Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) Ref. JEDEC Standard MS-026 80-Pin Dim Min Max Min A - 0.063 (1.60) A1 0.002 0.006 0.002 (0.05) (0.15) (0.05) A2 ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC 1 ...
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Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...
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Package Outlines Dim D General- (lead coplanarity) A Notes Not ...
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