MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 90

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
13.2.1
Six types of error conditions can be inserted into the transmit PCM30 data stream through register control bits
located at address Y01. These error events include the bipolar violation errors (BVE), CRC-4 errors (CRCE),
FAS errors (FASE), NFAS errors (NFSE), payload (PERR) and a loss of signal error (LOSE). The LOSE
function overrides the HDB3 encoding function (no BPV are added). Also included are E1 and E2 error bit
insertion on frames 13 and 15. See the bit descriptions (control register address Y01) for additional details.
13.2.2
There are 32 per timeslot control registers occupying a total of 32 unique addresses (Y90-YAF). Each register
controls a matching timeslot on the 32 transmit channels (onto the line) and the equivalent channel data on the
receive (DSTo) data. For example, register address Y91 of the first per timeslot control register contains
program control for transmit timeslot 1 and DSTo channel 1.
13.2.3
Any channel or combination of channels may be looped from transmit (sourced from DSTi) to receive (output
on DSTo) ST-BUS channels. When bit 4 (LTSL) in the Per Timeslot Control Word is set the data from the
equivalent transmit timeslot is looped back onto the equivalent receive channel.
Any channel or combination of channels may be looped from receive (sourced from the line data) to transmit
(output onto the line) channels. When bit 5 (RTSL) in the Per Timeslot Control Word is set the data from the
equivalent receive timeslot is looped back onto the equivalent transmit channel.
13.2.4
The MT9072 includes both a pseudo random bit sequence (PRBS) generator of type (2
PRBS generator (decoder), which operates on a bit sequence, and determines if it matches the transmitted
PRBS type (2
system debugging and testing without additional external hardware.
If control bit ADSEQ (register address Y01) is zero, any transmit (internal DSTi) timeslot or combination of
transmit timeslots may be connected to the PRBS generator. Timeslot n is selected by setting the TTSTn bit in
the Timeslot n Control Register (address Y90-YAF), where n is 0 to 31. Any data sent on DSTi is overwritten on
the selected timeslots.
Similarly, if control bit ADSEQ is zero, any DSTo receive timeslot or combination of receive timeslots may be
connected to the PRBS decoder. Timeslot n is selected by setting the RRSTn bit in the Timeslot n Control
Register (register address Y90-YAF), where n is 0 to 31. Data on DSTo is not affected.
PRBS data is distributed to the transmit channels sequentially one byte at a time. Consequently, the data
received must be in the same order that it was sent, in order for the PRBS decoder to correctly operate on the
data.
90
Register
Address
Y24
Y34
Y44
E1 Error Insertion
E1 Per Timeslot Control
E1 Per Timeslot Looping
E1 Pseudo-Random Bit Sequence (PRBS) Testing
Sync, CRC-4 remote alarm, MAS
Latched Status Register
Sync, CRC-4 Remote Alarm, MAS
Interrupt status register
Sync, CRC-4 Remote Alarm, MAS
Interrupt register mask
15
-1). Bits which don’t match are counted by an internal error counter. This provides for powerful
Table 47 - Registers Related to Maintenance and Alarms (E1)
Register
Latched version of receive CRC errors and synchronization loss
are available.
This register provides bits for interrupt generation for Y24 CRC
errors and synchronization loss functions.
This register provides bits for interrupt mask register for Y34.
Description
Advance Information
15
-1), and a reverse