MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 268

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
AC Electrical Characteristics - Receive Data Link Timing
268
RXDL
PCM 30
Bit Cells
E2i
Input
E4o - Note 1
(RxDLC Pin)
Output
RxBF
(Output)
Note 1 - The E4o signal is output at the RxDLC Pin when the E4CK control bit (address Y08) is set to one.
Note 2 - The PCM Timeslots are referred to RXDL Output which is delayed 4 bits from the RPOS/RNEG input.
Note3- The E4o Clock(RXDLC Output) is not a 50% duty cycle clock, it will be low for 25 % and high for 75% of the
4.096 MHz clock
RXDL
Bit Cells
E2i
RxDLC - Note 2
(Output)
RxDLC - Note 3
(Output)
RxDL
(Output)
Note 1 - RxDLC output applies for every second frame (RxBF) pulse (250us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
Note 4 - The PCM 30 Timeslots are with respect to RXDL Output
1
2
3
Clock Delay
Enable Delay
Data Delay Read
Characteristics
t
E4
H
W
t
ED
Figure 72 - Receive Basic Frame and E4o Timing
t
DDR
t
E4
L
W
Figure 73 - Receive Data Link Timing
Timeslot 31
Bit 8
Sym
Outputs Data
t
t
t
CD
t
CD
t
DDR
CD
ED
MT9072
t
BD
Min
t
CD
t
t
Typ
CD
ED
Max
125
55
55
Timeslot 0
Bit 1
Units
ns
ns
ns
t
BD
Preliminary Information
150pF load on RxDLC
150pF load on RxDLC
150pF load on RxDL
Test Conditions
V
V
V
T
T
T
V
V
V
V
T
T
T
T