MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 266

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MT9072

Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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MT9072
266
ST-BUS
Bit Cells
2Mb/s
ST-BUS
Bit Cells
8Mb/s
CKi
(ST-BUS C16i)
8Mb/s
CKi
(ST-BUS C4i)
2Mb/s
TxDLC - Note 2
(Output)
TxDLC - Note 3
(Output)
TxDL
(Input)
Note 1 - TxDLC output applies for every second frame (FPi) pulse (250us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
Figure 70 - Transmit Data Link Pin Timing
t
ED
t
CD
t
DS
Inputs Data
Preliminary Information
MT9072
t
CD
t
t
DH
ED
V
T
V
V
V
V
T
T
T
T

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