MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 26

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
Figure 1 -Functional Block Diagram ........................................................................................................................ 1
Figure 2 -Pin Connections (Jedec MS-026) .......................................................................................................... 10
Figure 3 -256 PIN LBGA (Jedec MO-192)............................................................................................................ 11
1.0
2.0
Figure 4 -PCM24 Link Frame Format (T1) ............................................................................................................ 40
Figure 5 -ST-BUS Format...................................................................................................................................... 40
Table 1 -ST-BUS vs. PCM24 Channel Relationship for 2.048 Mbit/s DST/CST Streams (T1) ............................. 41
Table 2 -ST-BUS Channel vs. PCM24 Channel Relationship for 8.192 Mbit/s DST/CST Streams (T1)............... 41
Table 3 -ST-BUS vs. PCM24 to Channel Relationship for IMA DST Streams (T1)............................................... 41
3.0
Table 4 -ST-BUS Channel vs. PCM30 Timeslot for 2.048 Mbit/s DST/CST Streams (E1) ................................... 43
Table 5 -ST-BUS Channel vs. PCM30 Timeslot Relationship for 8.192 Mbit/s DST/CST Streams (E1) .............. 43
Table 6 -PCM30 Timeslot to PCM30 Channel Relationship (E1).......................................................................... 43
Figure 6 -PCM30 Format (E1) ............................................................................................................................... 44
4.0
Table 7 -Registers Related to Framing Mode for the MT9072 (T1)....................................................................... 45
xxvi
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10 Performance Monitoring and Debugging................................................................................................ 39
2.1
2.2
2.3
2.4
3.1
3.2
4.1
4.1.1
Overview ........................................................................................................................ 38
PCM24 Interface (T1)..................................................................................................... 40
PCM30 Interface (E1)..................................................................................................... 42
Framing .......................................................................................................................... 44
Standards Compliance ........................................................................................................................... 38
Microprocessor Port ............................................................................................................................... 38
Interface to the Physical Layer Device ................................................................................................... 38
Interface to the System Backplane......................................................................................................... 38
Framing Modes ...................................................................................................................................... 38
Access to the Maintenance Channel...................................................................................................... 39
Robbed Bit Signaling/Channel Associated Signaling ............................................................................. 39
Common Channel Signaling................................................................................................................... 39
HDLCs.................................................................................................................................................... 39
T1 Interface to the System Backplane ................................................................................................... 40
E1 Interface to the System Backplane ................................................................................................... 42
E1 Interface to the Physical Layer Device.............................................................................................. 44
T1 Framing ............................................................................................................................................. 44
T1 Interface to the Physical Layer Device............................................................................................. 42
T1 Line Coding ...................................................................................................................................... 42
T1 Pulse Density ................................................................................................................................... 42
T1 D4 Framing................................................................................................................................. 45
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