MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 48
MT9072
Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9072.pdf
(278 pages)
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MT9072
4.2
The following Table shows the registers related to the E1 framing algorithm.
48
Register
Address
Y1A
Y2A
Y00
Y10
Y11
Y12
Y13
Y16
Y19
Y24
Y27
Y34
Y35
Y44
Y45
E1 Framing
Alarm and Framing Control
Register
Synchronization and Alarm
Status Word.
CRC-4 Timers and CRC-4 Local
Status
Alarm and Multiframe signaling
Status
NFAS and FAS Status Register
Loss of basic frame
synchronization counter
CRC-4 Error Counter
FAS Bit Counter and FAS Error
Counter.
Sync,CRC-4,MAS Latched
Status Register
Performance Presistent Latched
Status Register
CRC-4 Error Counter Latch.
Sync, CRC-4
Remote,Alarm,MAS and Phase
Status Register
Counter Indication and Counter
Overflow Interrupt status
Sync Interrupt Mask Register
Counter Indication and Counter
Overflow Interrupt Mask
Register
Register
Table 11 - Registers Related to Framing for MT9072 (E1)
This is the main register for selection of the framing mode. The
specific bits for control of the framer are CSYN, AUTY, CRCM,
REFRM, MFRF and AUTC
This register provides the real time status of receive basic frame
synchronization and receive multiframe synchronization. All bits in
this status register are relevant to framing except the slip bits.
All bits except the 2 sec timer are related to the reception of the
CRC-4 pattern in timeslot 0.
This register reports alarms such as AIS, loss of signal and
Timeslot 16 and 0 remote alarms. The bits of relevance for
framing are KLVE, LOSS,AIS16, AIS,RAI,RMA1 to 4, Y bit.
This register shows the FAS and NFAS status such as RFA 2 to 8
and RNFA.
This counter increments by one every 125 usec when the BSYNC
status is set to 1.
This error counter is incremented for each calculated CRC-4
submultiframe error. The CRCS1 and CRCS2 (Y11 bit 1 and 2)
events increment this counter.
This register reflects the FAS bit errors and a combined FAS
pattern error.
This register represents the latched version of framing status bits
such as BSYNC. These bits are set by changes in the associated
real time bits.
This register latches the detection of loss(LOSSP) and basic
frame sync(BSYNCP).
This a a sampled version of Y19 latched every one sec.
These are the interrupt status bits for BSYNC, Receive Multiframe
Alignment Interrupt etc.
This register represents the interrupt status bits for counter
overflows, counter indications etc.
This is the mask register for the events in register Y34.
This is the mask register for the events in register Y35
Description
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