MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 220

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
220
Bit
15
14
13
12
10
11
9
8
7
6
5
4
3
2
1
F3HVS
F3EVS
F3RVS
F3SVS
F2HVS
F2EVS
F2RVS
F2SVS
F1HVS
F1EVS
F1RVS
F1SVS
F0HVS
F0EVS
F0RVS
Name
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Framer 3 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(333) for framer are set. This bit can be masked and will remain low by the F3HM
bit in address 902.
Framer 3 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elasitc store register(336) or Elastic store status for Framer 3 are set. This bit can be
masked and will remain low by the F3EM bit in address 902.
Framer 3 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(335) for Framer 0 are set. This bit can be masked and will remain
low by the F3RM bit in address 902.
Framer 3 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync
status register(334) for Framer 3 are set. This bit can be masked and will remain low by the
F3SM bit in address 902.
Framer 2 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(233) or Elastic store status far Framer 2 are set. This bit can be masked and will
remain low by the F2HM bit in address 902.
Framer 2 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elastic status register(236) or Elastic store status for Framer 2 are set. This bit can be
masked and will remain low by the F2EM bit in address 902.
Framer 2 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(235) for Framer 2 are set. This bit can be masked and will remain
low by the F2RM bit in address 902.
Framer 2 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Counter status register(234) for Framer 2 are set. This bit can be masked and will remain low by
the F2SM bit in address 902.
Framer 1 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(133) or Elastic store status for Framer 1 are set. This bit can be masked and will
remain low by the F2HM bit in address 902.
Framer 1 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elasitc store register(136) or Elastic store status for Framer 1 are set. This bit can be
masked and will remain low by the F1EM bit in address 902.
Framer 1 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(135) for Framer 1 are set. This bit can be masked and will remain
low by theF1RM bit in address 902.
Framer 1 Sync Vector Status. This bit if unmasked is set if any of the bits in the Interrupt Sync
status register(134) for Framer 3 are set. This bit can be masked and will remain low by the
F1SM bit in address 902.
Framer 0 HDLC Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
HDLC register(033) or Elastic store status for Framer 0 are set. This bit can be masked and will
remain low by the F0HM bit in address 902.
Framer 0 Elastic Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Elasitc store register(036) or Elastic store status for Framer 0 are set. This bit can be
masked and will remain low by the F0EM bit in address 902.
Framer 0 Rx Line Vector Status. This bit if unmasked is set if any of the bits in the Interrupt
Receive Line status register(035) for Framer 0 are set. This bit can be masked and will remain
low by the F0RM bit in address 902.
Table 205 - Interrupt Vector 1 Status Register (R/W Address 910) (E1)
Functional Description
Advance Information