MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 272

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MT9072

Manufacturer Part Number
MT9072
Description
Octal T1-E1-J1 Framer
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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MT9072
17.1 AC Electrical Characteristics - PCM30 and ST-BUS Frame Format
In both the transmit and receive directions, PCM30 LSB maps to ST-BUS LSB.
272
E2i
2 Meg Clock
CLKE=1
E2i
2 Meg Clock
CLKE=0
RPOS
(Input)
(RZ Dual Rail)
RNEG
(Input)
(RZ Dual Rail)
RPOS
(Input)
(NRZ Dual Rail)
RNEG
(Input)
(NRZ Dual Rail)
RPOS
(Input)
(NRZ Single Rail)
RNEG
(Input)
(NRZ Single Rail)
PCM30 Receive
Bit Cells(Neg Edge)
(Sample Data)
ClKE selection is noly applicable for NRZ mode
FRAME
15
FRAME
Significant
Bit (First)
0
Most
TIMESLOT
Figure 78 - PCM30 Receive Functional Timing
BIT
0
1
(1)
• • • • • • • •
BIT
2
TIMESLOT
Figure 79 - PCM 30 Format
1
BIT
3
2.0 ms
BIT
(8/2.048) s
4
(0)
• • • •
BIT
5
125 s
BIT
6
FRAME
14
(1)
BIT
7
TIMESLOT
BIT
30
8
Preliminary Information
FRAME
15
Least
Significant
Bit (Last)
TIMESLOT
(1)
31
FRAME
0

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