MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 116

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
116
15-10
3-2
1-0
Bit
9
8
7
6
5
4
CSIGEN
not used
SIP1-0
SM1-0
RBEN
RSDB
Name
RFL
(00)
(0)
(0)
(0)
(0)
#
#
not used.
Common Channel Signaling Enable. Setting this bit enables common channel signaling in
conjunction with register Y0B. All other channels on the CSTo stream are tristate. Register
Y0B defines the map between CST and PCM stream.
Robbed Bit Signaling Enable. Setting this bit multiplexes the AB or ABCD signaling bits
into bit position 8 of all DS0 channels every 6th frame. Signaling is only sent in channels for
which the CC bit in the per channel control word (Address Y90 - YA7) is set to 1.
Receive Signaling Debounce. Setting this bit causes incoming signaling bits to be
debounced for a period of 6 to 9 milliseconds before reporting on CSTo streams or in the
Receive signaling Bits Registers..
Receive Signaling Freeze Due to Loss. If one, the receive signaling is frozen if a receive
loss of signal is detected. The freeze is cleared upon clearance of Loss.
not used.
Signaling Message. These two bits are used to fill the vacant bit positions available on
CSTo when the MT9072 is operating on a D4 trunk. The first two bits of each reporting
nibble of CSTo contain the AB signaling bits. The last two will contain SM1 and SM0 (in that
order). When the MT9072 is connected to ESF trunks four signaling bits (ABCD) are
reported and the bits SM1-0 settings are ignored.
Signaling Interrupt Period. These 2 bits determine the signaling Interrupt period due to the
Receive signaling changes. This 2 bits determine the duration of the signaling interrupt bit
CASRI(Y35).
00
01
10
2 Msec Period
8 Msec Period
16 Msec Period
Table 68 - Signaling Control Word (Y04) (T1)
Functional Description
Advance Information