MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 178

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
178
15-8
Bit
15-8
7-0
Bit
7-0
1
0
Bit
TXIDC
RXIDC
Name
Name
Name
DLCK
E4CK
7-0
(0)
7-0
(0)
#
(0)
(0)
#
not used.
Transmit Idle Code. This is the idle code that is sent on the PCM30 channels if the per timeslot
control bit MPDT is set(Y90-YAF)
not used.
Receive Idle Code. This is the idle code that is sent on the DSTochannels if the per timeslot
control bit MPDR is set(Y90-YAF). Note that bit 7 is sent out first.
Extracted 4 Data Link Clock. If one, the RxDLC pin outputs an ST-BUS type 4.096MHz clock
signal derived from a doubled 2.048MHz clock signal at the EXCLi pin. This clock is
synchronous with the receive data before it passes through the elastic buffer at the RxDL pin,
or at the DSTo pin if control bit ELAS (register address Y03) is disabled. See Figure 32. If zero,
the RxDLC pin operates as a receive data link clock or enable signal as programmed by
control bit DLCK (register address Y08).
Data Link Clock. If one, the TxDLC and RxDLC pins output a gapped clock. If zero, the
TxDLC and RxDLC pins output an active low enable signal. The above only applies for the
national bits enabled for DL pin operation (by the Sa4-8 bits of register address Y03). See
Figures 30 to 34.
Table 155 - DataLink Control Register (R/W Address Y08) (E1)
Table 157 - Transmit Idle Code Register(Y0A) (E1)
Table 156 - Receive Idle Code Register(Y09) (E1)
Functional Description
Functional Description
Functional Description
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