MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 35

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
Table 190 -Channel n, Transmit CAS Data Register (Address Y51-Y6F) (E1) ................................................... 207
Table 191 -Channel n, Receive CAS Data Register (Address Y71-Y8F)............................................................ 208
Table 192 -Timeslot (TS) n (n = 0 to 31) Control Register (Address Y90 (TS0) to YAF(TS31)) (E1).................. 209
Table 193 -Transmit National Bits (Sa4 - Sa8) TNn (n = 0 to 4) Data Register
Table 194 -Receive National Bits (Sa4 - Sa8) RNn
Table 195 -HDLC Control1(YF2) (E1) ................................................................................................................. 212
Table 196 -HDLC Test Control(YF3) (E1) ........................................................................................................... 213
Table 197 -TX Fifo Write Register(YF5) (E1) ...................................................................................................... 213
Table 198 -TX Byte Count Register(YF6) (E1).................................................................................................... 214
Table 199 -Global Control0 Register (R/W Address 900) (E1)............................................................................ 215
Table 200 -Global Control1 Register (R/W Address 901) (E1)............................................................................ 215
Table 201 -Interrupt Vector 1 Mask Register (R/W Address 902) (E1) ............................................................... 216
Table 202 -Interrupt Vector 2 Mask Register (R/W Address 903) (E1) ............................................................... 217
Table 203 -Framer Loopback Global Register(904) (E1) .................................................................................... 219
Table 204 -Framer 0 ST-Bus Interrupt Vector Mask(905) (E1) ........................................................................... 219
Table 205 -Interrupt Vector 1 Status Register (R/W Address 910) (E1).............................................................. 220
Table 206 -Interrupt Vector 2 Status Register (Address 911) (E1)...................................................................... 221
Table 207 -Identification Revision Code Data Register (R Address 912) (E1) .................................................... 222
Table 208 - ST-Bus Analyszer Vector Status Register (Address 913) (E1) ....................................................... 222
Table 209 -ST-BUS Analyser Data (Address 920-93F) (E1)............................................................................... 222
17.0 Applications ................................................................................................................. 223
Figure 11 -8 T1/E1 Links with Synchronous Common Channel Signaling .......................................................... 223
Figure 12 -8 T1/E1 Links with Synchronous Data Link Signaling........................................................................ 224
Figure 13 -8 T1/E1 Links with Asynchronous Data Link Signaling ...................................................................... 225
Figure 14 -8 T1/E1 Links with no JA or PLL in LIU, Slave or Master Mode, Jitter-Free ST-BUS........................ 226
Figure 15 -8 T1/E1 Links with ATM IMA.............................................................................................................. 227
Figure 16 -8 T1/E1 Links with Asynchronous ST-BUS........................................................................................ 228
Figure 17 -DS3 (44Mb/s) Mux Cross Connect with 28 Asynchronous T1 Links.................................................. 229
Figure 18 -DS3 (44Mb/s) Mux Concentrator with 28 Asynchronous T1 Links..................................................... 230
Figure 19 -E3 (34Mb/s) MUX Cross Connect with 16 Asynchronous E1 Links................................................... 231
Figure 20 -E3 (34Mb/s) MUX Concentrator to 16 Asynchronous E1 Links ......................................................... 232
(R/W Address YB0 to YB4) (E1)......................................................................................................................... 210
(n = 0 to 4) Data Register (R/W Address YC0 to YC4) (E1)............................................................................... 211
16.2.8 Transmit CAS (ABCD) Data Registers (Y51 - Y6F) Bit Functions................................................. 207
16.2.9 Receive CAS (ABCD) Data Registers (Y71 - Y8F) Bit Functions.................................................. 208
16.2.10 Timeslot 0-31 Control Registers (Y90 - YAF) Bit Functions .......................................................... 209
16.2.11
16.2.12
16.2.13
16.2.14 Global Control and Status Registers(900-91F) Bit Functions........................................................ 215
Transmit National Bit RN Data Registers (YB0- YB4) Bit Functions.......................................... 210
Receive National Bit RN Data Registers (YC0- YC4) Bit Functions .......................................... 211
Master Control Registers (YF0 - YF6) Bit Functions.................................................................. 212
Table of Contents (continued)
MT9072
xxxv