MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 100

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

MT9072
15.1 Test Access Port (TAP)
The Test Access Port (TAP) provides access to the many test functions of the MT9072. It consists of four input
pins and one output pin. The following pins are from the TAP.
Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK signal does not interfere with any
on-chip clocks and thus remains independent. The TCK permits shifting of test data into or out of the
Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-
chip logic.
Test Mode Select Input (TMS) - The logic signals received at the TMS input are interpreted by the TAP
Controller to control the test operations. The TMS signal is sampled at the rising edge of the TCK pulses. This
pin is internally pulled up to device V
Test Data Input (TDI) - Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This
pin is internally pulled up to device V
Test Data Output (TDO) - Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDO pin. The data out of TDO
is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the
TDO driver is set to a high impedance state.
Test Reset (TRST) - Reset the JTAG scan structure.
100
Framer
Input
Pins
TRST
TDO
TMS
TCK
TDI
TAP
Figure 10 - Boundary Scan Test Circuit Block Diagram
Controller
DD
DD
TAP
when it is not driven from an external source.
when it is not driven from an external source.
Instruction Register
Test Data Registers
Device ID Register
Bypass Register
Boundary Scan
Register
Framer
Logic
Core
Advance Information
Framer
Output
Pins