MT9072 Zarlink Semiconductor, Inc., MT9072 Datasheet - Page 79

• Manufacturer Part Number: MT9072
• Description: Octal T1-E1-J1 Framer
• Manufacturer: Zarlink Semiconductor, Inc.

Advance Information
9.1.5.3 IEEE 1149.1-1990 Test Access Port (TAP)
Five signals (TDI, TDO, TMS, TCK & TRST) make up the Test Access Port (TAP) of the IEEE 1149.1-1990
Standard Test Port and Boundary-Scan Architecture. The TAP provides access to test support functions built
into the MT9072. The TAP is also referred to as a JTAG (Joint Test Action Group) port. See the JTAG section
for additional details.
9.1.6
Dedicated data link pins are included which provide the user the option of bypassing the receive elastic buffer
and accessing timeslot 0 data link (DL) data with an external controller. The MT9072 provides numerous
additional methods for accessing the DL, refer to the DL sections for details.
9.1.7
Dedicated multiframe boundary pins are included which provide the user the option of setting the multiframe
boundaries and identifying the multiframe boundaries with an external device. Refer to the RxMF and TxMF pin
descriptions for more details.
10.0 ST-BUS Analyzer
The ST-BUS Analyzer is a powerful system diagnostic and debugging tool. The ST-BUS Analyzer allows for the
capture of any ST-BUS data stream or channel to a 32 byte memory. The ST-BUS Analyzer can capture a
single frame of data or 32 samples of a specified channel from DSTi, DSTo, CSTi or CSTo from any one of the
8 framers. The analysis can be performed continuously or on a single shot basis where 32 bytes are captured
and then the analysis is suspended. An optional interrupt can be generated when a single shot analysis is
complete. The operation of the ST-BUS analyzer is controlled by Global Control Register 1 (901).
11.0 Loopbacks
11.1 T1 Loopbacks
In order to meet PRI Layer 1 requirements and to assist in circuit fault sectionalization, the MT9072 has 7
loopback functions.
The control bits for digital, remote, ST-BUS and payload loopbacks are located at address Y05. The remote
and local timeslot loopbacks are controlled through control bits of the Timeslot Control register located at
addresses Y90-YA7.
a) Digital loopback (DG Loop) - DSTi to DSTo at the PCM24 side. Bit DLBK = 0 normal; DLBK = 1 activate.
b) Payload loopback (PL Loop) - Payload loopback (DSTo to DSTi). Bit PLBK = 0 normal; PLBK = 1 activate.
The payload loopback is effectively a physical connection of DSTo to DSTi within the framer.
Note: Set RxDO (YF1 bit 9 to 1) to obtain correct data at the Tx.
System
System
Multiframe Boundary (RxMF, TxMF Pins)
Data Link (DL) Interface (RxDL, RxDLC, TxDL, TxDLC Pins)
DSTo
DSTo
DSTi
DSTi
MT9072
MT9072
Tx
Rx
Tx
PCM24
PCM24
MT9072
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